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326769-002 参数 Datasheet PDF下载

326769-002图片预览
型号: 326769-002
PDF下载: 下载PDF文件 查看货源
内容描述: 移动第三代英特尔®科雷亚?? ¢处理器家族 [Mobile 3rd Generation Intel® Core™ Processor Family]
分类和应用:
文件页数/大小: 342 页 / 2513 K
品牌: INTEL [ INTEL ]
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Processor Configuration Registers  
2.5.15  
PAVPC—Protected Audio Video Path Control Register  
All the bits in this register are locked by Intel TXT. When locked, the RW bits are RO.  
B/D/F/Type:  
Address Offset:  
Reset Value:  
Access:  
0/0/0/PCI  
58–5Bh  
00000000h  
RW-L, RW-KL  
32 bits  
Size:  
Reset  
Value  
RST/  
PWR  
Bit  
Access  
Description  
31:3  
RO  
0h  
0b  
0h  
Reserved (RSVD)  
PAVP Lock (PAVPLCK)  
This bit will lock all writeable contents in this register when set  
(including itself). Only a hardware reset can unlock the register  
again.  
For the processor, this Lock bit needs to be set only if PAVP is  
enabled (bit_PAVPE = '1`).  
2
RW-KL  
Uncore  
1:0  
RO  
Reserved (RSVD)  
2.5.16  
DPR—DMA Protected Range Register  
DMA protected range register.  
B/D/F/Type:  
Address Offset:  
Reset Value:  
Access:  
0/0/0/PCI  
5C–5Fh  
00000000h  
RW-L, RO-V, RW-KL  
32 bits  
Size:  
BIOS Optimal Default  
000h  
Reset  
Value  
RST/  
PWR  
Bit  
Access  
Description  
31:3  
RO  
0h  
Reserved (RSVD)  
Enable Protected Memory (EPM)  
This field controls DMA accesses to the DMA Protected Range  
(DPR) region.  
0 = DPR is disabled  
1 = DPR is enabled. All DMA requests accessing DPR region are  
blocked.  
Hardware reports the status of DPR enable/disable through the  
PRS field in this register.  
2
RW-L  
0b  
Uncore  
Uncore  
Protected Region Status (PRS)  
This field indicates the status of DPR.  
0 = DPR protection disabled  
1
0
RO-V  
RO  
0b  
0h  
1 = DPR protection enabled  
Reserved (RSVD)  
Datasheet, Volume 2  
59