Processor Configuration Registers
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/PCI
54–57h
0000209Fh
RW-L, RO, RW
32 bits
Size:
BIOS Optimal Default
000000h
Reset
Value
RST/
PWR
Bit
Access
Description
Device 4 Enable (D4EN)
0 = Bus 0 Device 4 is disabled and not visible.
1 = Bus 0 Device 4 is enabled and visible.
This bit will be set to 0b and remain 0b if Device 4 capability is
disabled.
7
6:5
4
RW-L
RO
1b
0h
1b
Uncore
Reserved (RSVD)
Internal Graphics Engine (D2EN)
0 = Bus 0 Device 2 is disabled and hidden
1 = Bus 0 Device 2 is enabled and visible
This bit will be set to 0b and remain 0b if Device 2 capability is
disabled.
RW-L
Uncore
Uncore
PEG10 Enable (D1F0EN)
0 = Bus 0 Device 1 Function 0 is disabled and hidden.
1 = Bus 0 Device 1 Function 0 is enabled and visible.
This bit will be set to 0b and remain 0b if PEG10 capability is
disabled.
3
2
RW-L
RW-L
1b
1b
PEG11 Enable (D1F1EN)
0 = Bus 0 Device 1 Function 1 is disabled and hidden.
1 = Bus 0 Device 1 Function 1 is enabled and visible.
This bit will be set to 0b and remain 0b if:
Uncore
•
•
PEG11 capability is disabled by fuses, OR
PEG11 is disabled by strap (PEG0CFGSEL)
PEG12 Enable (D1F2EN)
0 = Bus 0 Device 1 Function 2 is disabled and hidden.
1 = Bus 0 Device 1 Function 2 is enabled and visible.
This bit will be set to 0b and remain 0b if:
1
0
RW-L
RO
1b
1b
Uncore
Uncore
•
•
PEG12 capability is disabled by fuses, OR
PEG12 is disabled by strap (PEG0CFGSEL)
Host Bridge (D0EN)
Bus 0 Device 0 Function 0 may not be disabled and is therefore
hardwired to 1.
58
Datasheet, Volume 2
INTEL [ INTEL ]
