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326769-002 参数 Datasheet PDF下载

326769-002图片预览
型号: 326769-002
PDF下载: 下载PDF文件 查看货源
内容描述: 移动第三代英特尔®科雷亚?? ¢处理器家族 [Mobile 3rd Generation Intel® Core™ Processor Family]
分类和应用:
文件页数/大小: 342 页 / 2513 K
品牌: INTEL [ INTEL ]
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Processor Configuration Registers  
B/D/F/Type:  
Address Offset:  
Reset Value:  
Access:  
0/0/0/PCI  
50–51h  
0028h  
RW-L, RW-KL  
16 bits  
Size:  
BIOS Optimal Default  
00h  
Reset  
Value  
RST/  
PWR  
Bit  
Access  
Description  
2
RO  
0h  
Reserved (RSVD)  
IGD VGA Disable (IVD)  
0 = Enable. Device 2 (IGD) claims VGA memory and I/O cycles,  
the Sub-Class Code within Device 2 Class Code register is  
00.  
1 = Disable. Device 2 (IGD) does not claim VGA cycles (Memory  
and I/O), and the Sub- Class Code field within Device 2  
Function 0 Class Code register is 80.  
BIOS Requirement: BIOS must not set this bit to 0 if the GMS  
field (bits 7:3 of this register) pre-allocates no memory.  
1
RW-L  
0b  
Uncore  
This bit MUST be set to 1 if Device 2 is disabled either using a  
fuse or fuse override (CAPID0_A[IGD] = 1) or using a register  
(DEVEN[3] = 0).  
This register is locked by Intel TXT lock.  
0 = Enable  
1 = Disable  
GGC Lock (GGCLCK)  
When set to 1b, this bit will lock all bits in this register.  
0
RW-KL  
0b  
Uncore  
2.5.14  
DEVEN—Device Enable Register  
This register allows for enabling/disabling of PCI devices and functions that are within  
the processor package. The following table bit definitions describe the behavior of all  
combinations of transactions to devices controlled by this register.  
All the bits in this register are Intel TXT Lockable.  
B/D/F/Type:  
Address Offset:  
Reset Value:  
Access:  
0/0/0/PCI  
54–57h  
0000209Fh  
RW-L, RO, RW  
32 bits  
Size:  
BIOS Optimal Default  
000000h  
Reset  
Value  
RST/  
PWR  
Bit  
Access  
Description  
31:15  
RO  
0h  
Reserved (RSVD)  
Chap Enable (D7EN)  
0 = Bus 0 Device 7 is disabled and not visible.  
1 = Bus 0 Device 7 is enabled and visible.  
Non-production BIOS code should provide a setup option to  
enable Bus 0 Device 7. When enabled, Bus 0 Device 7 must be  
initialized in accordance to standard PCI device initialization  
procedures.  
14  
RW  
0b  
Uncore  
Uncore  
PEG60 Enable (D6F0EN)  
0 = Bus 0 Device 6 Function 0 is disabled and hidden.  
1 = Bus 0 Device 6 Function 0 is enabled and visible.  
This bit will be set to 0b and remain 0b if PEG60 capability is  
disabled.  
13  
RW-L  
RO  
1b  
0h  
12:8  
Reserved (RSVD)  
Datasheet, Volume 2  
57