Processor Configuration Registers
The processor also forwards accesses to the Legacy VGA I/O ranges according to the
settings in the PEG configuration registers BCTRL (VGA Enable) and PCICMD (IOAE),
unless a second adapter (monochrome) is present on the DMI Interface/PCI (or ISA).
The presence of a second graphics adapter is determined by the MDAP configuration
bit. When MDAP is set, the processor will decode legacy monochrome I/O ranges and
forward them to the DMI Interface. The I/O ranges decoded for the monochrome
adapter are 3B4h, 3B5h, 3B8h, 3B9h, 3BAh, and 3BFh.
Note:
The PEG I/O address range registers defined above are used for all I/O space allocation
for any devices requiring such a window on PCI Express.
The PCICMD register can disable the routing of I/O cycles to PCI Express.
2.3.12
MCTP and KVM Flows
Refer to THE DMI2 specification for details.
MCTP cycles are not processed within the processor. MCTP cycles are merely passed
from input port to destination port based on routing ID.
2.3.13
Decode Rules and Cross-Bridge Address Mapping
2.3.13.1
DMI Interface Decode Rules
All “SNOOP semantic” PCI Express transactions are kept coherent with processor
caches.
All “Snoop not required semantic” cycles must reference the main DRAM address
range. PCI Express non-snoop initiated cycles are not snooped.
The processor accepts accesses from DMI Interface to the following address ranges:
• All snoop memory read and write accesses to Main DRAM including PAM region
(except stolen memory ranges, TSEG, A0000h–BFFFFh space)
• Write accesses to enabled VGA range, MBASE/MLIMIT, and PMBASE/PMLIMIT will
be routed as peer cycles to the PCI Express interface.
• Write accesses above the top of usable DRAM and below 4 GB (not decoding to PCI
Express or GMADR space) will be treated as master aborts.
• Read accesses above the top of usable DRAM and below 4 GB (not decoding to PCI
Express) will be treated as unsupported requests.
• Reads and accesses above the TOUUD will be treated as unsupported requests on
VC0/VCp.
DMI Interface memory read accesses that fall between TOLUD and 4 GB are considered
invalid and will master abort. These invalid read accesses will be reassigned to address
000C_0000h and dispatch to DRAM. Reads will return unsupported request completion.
Writes targeting PCI Express space will be treated as peer-to-peer cycles.
There is a known usage model for peer writes from DMI to PEG. A video capture card
can be plugged into the PCH PCI bus. The video capture card can send video capture
data (writes) directly into the frame buffer on an external graphics card (writes to the
PEG port). As a result, peer writes from DMI to PEG must be supported.
I/O cycles and configuration cycles are not supported in the upstream direction. The
result will be an unsupported request completion status.
Datasheet, Volume 2
39
INTEL [ INTEL ]
