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326769-002 参数 Datasheet PDF下载

326769-002图片预览
型号: 326769-002
PDF下载: 下载PDF文件 查看货源
内容描述: 移动第三代英特尔®科雷亚?? ¢处理器家族 [Mobile 3rd Generation Intel® Core™ Processor Family]
分类和应用:
文件页数/大小: 342 页 / 2513 K
品牌: INTEL [ INTEL ]
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Processor Configuration Registers  
2.3.11  
I/O Address Space  
The system agent generates either DMI Interface or PCI Express bus cycles for all  
processor I/O accesses that it does not claim. Configuration Address Register  
(CONFIG_ADDRESS) and the Configuration Data Register (CONFIG_DATA) are used to  
generate PCI configuration space access.  
The processor allows 64K+3 bytes to be addressed within the I/O space. The upper 3  
locations can be accessed only during I/O address wrap-around when address bit 16 is  
asserted. Address bit 16 is asserted on the processor bus whenever an I/O access is  
made to 4 bytes from address 0FFFDh, 0FFFEh, or 0FFFFh. Address bit 16 is also  
asserted when an I/O access is made to 2 bytes from address 0FFFFh.  
A set of I/O accesses are consumed by the internal graphics device if it is enabled. The  
mechanisms for internal graphics I/O decode and the associated control is explained  
later.  
The I/O accesses are forwarded normally to the DMI Interface bus unless they fall  
within the PCI Express I/O address range as defined by the mechanisms explained  
below. I/O writes are NOT posted. Memory writes to PCH or PCI Express are posted.  
The PCI Express devices have a register that can disable the routing of I/O cycles to the  
PCI Express device.  
The processor responds to I/O cycles initiated on PCI Express or DMI with an UR status.  
Upstream I/O cycles and configuration cycles should never occur. If one does occur, the  
transaction will complete with an UR completion status.  
I/O reads that lie within 8-byte boundaries but cross 4-byte boundaries are issued from  
the processor as 1 transaction. It will be divided into 2 separate transactions. I/O writes  
that lie within 8-byte boundaries but cross 4-byte boundaries will be split into 2  
transactions by the processor.  
2.3.11.1  
PCI Express* I/O Address Mapping  
The processor can be programmed to direct non-memory (I/O) accesses to the PCI  
Express bus interface when processor initiated I/O cycle addresses are within the PCI  
Express I/O address range. This range is controlled using the I/O Base Address  
(IOBASE) and I/O Limit Address (IOLIMIT) registers in Device 1 Functions 0, 1, 2 or  
Device 6 configuration space.  
Address decoding for this range is based on the following concept. The top 4 bits of the  
respective I/O Base and I/O Limit registers correspond to address bits A[15:12] of an  
I/O address. For the purpose of address decoding, the device assumes that lower  
12 address bits A[11:0] of the I/O base are zero and that address bits A[11:0] of the  
I/O limit address are FFFh. This forces the I/O address range alignment to 4 KB  
boundary and produces a size granularity of 4 KB.  
The processor positively decodes I/O accesses to PCI Express I/O address space as  
defined by the following equation:  
I/O_Base_Address processor I/O Cycle Address I/O_Limit_Address  
The effective size of the range is programmed by the plug-and-play configuration  
software and it depends on the size of I/O space claimed by the PCI Express device.  
38  
Datasheet, Volume 2