欢迎访问ic37.com |
会员登录 免费注册
发布采购

326769-002 参数 Datasheet PDF下载

326769-002图片预览
型号: 326769-002
PDF下载: 下载PDF文件 查看货源
内容描述: 移动第三代英特尔®科雷亚?? ¢处理器家族 [Mobile 3rd Generation Intel® Core™ Processor Family]
分类和应用:
文件页数/大小: 342 页 / 2513 K
品牌: INTEL [ INTEL ]
 浏览型号326769-002的Datasheet PDF文件第32页浏览型号326769-002的Datasheet PDF文件第33页浏览型号326769-002的Datasheet PDF文件第34页浏览型号326769-002的Datasheet PDF文件第35页浏览型号326769-002的Datasheet PDF文件第37页浏览型号326769-002的Datasheet PDF文件第38页浏览型号326769-002的Datasheet PDF文件第39页浏览型号326769-002的Datasheet PDF文件第40页  
Processor Configuration Registers  
2.3.7  
Graphics Memory Address Ranges  
The integrated memory controller can be programmed to direct memory accesses to  
IGD when addresses are within any of two ranges specified using registers in MCH  
Device 2 configuration space.  
1. The Graphics Memory Aperture Base Register (GMADR) is used to access graphics  
memory allocated using the graphics translation table.  
2. The Graphics Translation Table Base Register (GTTADR) is used to access the  
translation table and graphics control registers. This is part of GTTMMADR register.  
These ranges can reside above the Top-of-Low-DRAM and below High BIOS and APIC  
address ranges. They MUST reside above the top of memory (TOLUD) and below 4 GB  
so they do not steal any physical DRAM memory space.  
Alternatively, these ranges can reside above 4 GB, similar to other BARs which are  
larger than 32 bits in size.  
GMADR is a Prefetchable range in order to apply USWC attribute (from the processor  
point of view) to that range. The USWC attribute is used by the processor for write  
combining.  
2.3.7.1  
IOBAR Mapped Access to Device 2 MMIO Space  
Device 2, integrated graphics device, contains an IOBAR register. If Device 2 is  
enabled, then IGD registers or the GTT table can be accessed using this IOBAR. The  
IOBAR is composed of an index register and a data register.  
MMIO_Index: MMIO_INDEX is a 32 bit register. A 32-bit (all bytes enabled) I/O write  
to this port loads the offset of the MMIO register or offset into the GTT that needs to be  
accessed. An I/O Read returns the current value of this register. I/O read/write  
accesses less than 32 bits in size (all bytes enabled) will not target this register.  
MMIO_Data: MMIO_DATA is a 32 bit register. A 32 bit (all bytes enabled) I/O write to  
this port is re-directed to the MMIO register pointed to by the MMIO-index register. An  
I/O read to this port is re-directed to the MMIO register pointed to by the MMIO-index  
register. I/O read/write accesses less than 32 bits in size (all bytes enabled) will not  
target this register.  
The result of accesses through IOBAR can be:  
• Accesses directed to the GTT table (that is, route to DRAM).  
• Accesses to internal graphics registers with the device.  
• Accesses to internal graphics display registers now located within the PCH (that is,  
route to DMI).  
Note:  
GTT table space writes (GTTADR) are supported through this mapping mechanism.  
This mechanism to access internal graphics MMIO registers must not be used to access  
VGA I/O registers that are mapped through the MMIO space. VGA registers must be  
accessed directly through the dedicated VGA I/O ports.  
2.3.7.2  
Trusted Graphics Ranges  
No trusted graphics ranges are supported.  
36  
Datasheet, Volume 2