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326769-002 参数 Datasheet PDF下载

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型号: 326769-002
PDF下载: 下载PDF文件 查看货源
内容描述: 移动第三代英特尔®科雷亚?? ¢处理器家族 [Mobile 3rd Generation Intel® Core™ Processor Family]
分类和应用:
文件页数/大小: 342 页 / 2513 K
品牌: INTEL [ INTEL ]
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Processor Configuration Registers  
2.3.4.2  
Indirect Accesses to MCHBAR Registers  
Similar to prior chipsets, MCHBAR registers can be indirectly accessed using:  
• Direct MCHBAR access decode:  
Cycle to memory from processor  
Hits MCHBAR base, AND  
MCHBAR is enabled, AND  
Within MMIO space (above and below 4 GB)  
• GTTMMADR (10000h–13FFFh) range -> MCHBAR decode:  
Cycle to memory from processor, AND  
Device 2 (IGD) is enabled, AND  
Memory accesses for Device 2 is enabled, AND  
Targets graphics MMIO Function 0, AND  
MCHBAR is enabled or cycle is a read. If MCHBAR is disabled, only read  
access is allowed.  
• MCHTMBAR -> MCHBAR (Thermal Monitor)  
Cycle to memory from processor, AND  
AND Targets MCHTMBAR base  
• IOBAR -> GTTMMADR -> MCHBAR.  
— Follows IOBAR rules. See GTTMMADR information above as well.  
2.3.4.3  
2.3.4.4  
Memory Remapping  
An incoming address (referred to as a logical address) is checked to see if it falls in the  
memory re-map window. The bottom of the re-map window is defined by the value in  
the REMAPBASE register. The top of the re-map window is defined by the value in the  
REMAPLIMIT register. An address that falls within this window is remapped to the  
physical memory starting at the address defined by the TOLUD register. The TOLUD  
register must be 1M aligned.  
Hardware Remap Algorithm  
The following pseudo-code defines the algorithm used to calculate the DRAM address to  
be used for a logical address above the top of physical memory made available using  
re-claiming.  
IF (ADDRESS_IN[38:20] REMAP_BASE[35:20]) AND  
(ADDRESS_IN[38:20] REMAP_LIMIT[35:20]) THEN  
ADDRESS_OUT[38:20] = (ADDRESS_IN[38:20] – REMAP_BASE[35:20]) +  
0000000b & TOLUD[31:20]  
ADDRESS_OUT[19:0] = ADDRESS_IN[19:0]  
Datasheet, Volume 2  
29