Processor Configuration Registers
Figure 2-4. PCI Memory Address Range
4 GB
FFFF_FFFFh
FFE0_0000h
High BIOS
4 GB – 2 MB
DMI Interface
(subtractive decode)
FEF0_0000h
4 GB – 17 MB
4 GB – 18 MB
4 GB – 19 MB
MSI Interrupts
FEE0_0000h
FED0_0000h
DMI Interface
(subtractive decode)
Local (CPU) APIC
I/O APIC
FEC8_0000h
FEC0_0000h
4 GB – 20 MB
4 GB – 256 MB
DMI Interface
(subtractive decode)
F000_0000h
Possible
address range/
size (not
PCI Express* Configuration
Space
ensured)
E000_0000h
4 GB – 512 MB
BARs, Internal
Graphics
DMI Interface
(subtractive decode)
ranges, PCI
Express* Port,
CHAPADR could
be here.
TOLUD
2.3.3.1
APIC Configuration Space (FEC0_0000h – FECF_FFFFh)
This range is reserved for APIC configuration space. The I/O APIC(s) usually reside in
the PCH portion of the chipset, but may also exist as stand-alone components like PXH.
The IOAPIC spaces are used to communicate with IOAPIC interrupt controllers that
may be populated in the system. Since it is difficult to relocate an interrupt controller
using plug-and-play software, fixed address decode regions have been allocated for
them. Processor accesses to the default IOAPIC region (FEC0_0000h to FEC7_FFFFh)
are always forwarded to DMI.
The processor optionally supports additional I/O APICs behind the PCI Express
“Graphics” port. When enabled using the APIC_BASE and APIC_LIMIT registers
(mapped PCI Express Configuration space offset 240h and 244h), the PCI Express
port(s) will positively decode a subset of the APIC configuration space.
26
Datasheet, Volume 2
INTEL [ INTEL ]
