Processor Configuration Registers
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®
2.3.2.7
Intel Management Engine (Intel ME) UMA
Intel ME (the AMT Intel Management Engine) can be allocated UMA memory. Intel
MEmemory is “stolen” from the top of the Host address map. The Intel ME stolen
memory base is calculated by subtracting the amount of memory stolen by the Intel
Management Engine from TOM.
Only Intel ME can access this space; it is not accessible by or coherent with any
processor side accesses.
2.3.3
PCI Memory Address Range (TOLUD – 4 GB)
This address range, from the top of low usable DRAM (TOLUD) to 4 GB is normally
mapped to the DMI Interface.
Device 0 exceptions are:
1. Addresses decoded to the egress port registers (PXPEPBAR)
2. Addresses decoded to the memory mapped range for internal MCH registers
(MCHBAR)
3. Addresses decoded to the registers associated with the MCH/PCH Serial
Interconnect (DMI) register memory range (DMIBAR)
For each PCI Express port, there are two exceptions to this rule:
1. Addresses decoded to the PCI Express Memory Window defined by the MBASE,
MLIMIT, registers are mapped to PCI Express.
2. Addresses decoded to the PCI Express prefetchable Memory Window defined by the
PMBASE, PMLIMIT, registers are mapped to PCI Express
In integrated graphics configurations, there are exceptions to this rule:
1. Addresses decoded to the internal graphics translation window (GMADR)
2. Addresses decoded to the internal graphics translation table or IGD registers
(GTTMMADR)
In a VT enabled configuration, there are exceptions to this rule:
1. Addresses decoded to the memory mapped window to Graphics VT remap engine
registers (GFXVTBAR)
2. Addresses decoded to the memory mapped window to DMI VC1 VT remap engine
registers (DMIVC1BAR)
3. Addresses decoded to the memory mapped window to PEG/DMI VC0 VT remap
engine registers (VTDPVC0BAR)
4. TCm accesses (to Intel ME stolen memory) from PCH do not go through VT remap
engines.
Some of the MMIO Bars may be mapped to this range or to the range above TOUUD.
There are sub-ranges within the PCI Memory address range defined as APIC
Configuration Space, MSI Interrupt Space, and High BIOS Address Range. The
exceptions listed above for internal graphics and the PCI Express ports Must Not
overlap with these ranges.
Datasheet, Volume 2
25
INTEL [ INTEL ]
