Processor Configuration Registers
2.3.4.5
Programming Model
The memory boundaries of interest are:
• Bottom of Logical Address Remap Window defined by the REMAPBASE register,
which is calculated and loaded by BIOS.
• Top of Logical Address Remap Window defined by the REMAPLIMIT register, which
is calculated and loaded by BIOS.
• Bottom of Physical Remap Memory defined by the existing TOLUD register.
• Top of Physical Remap Memory, which is implicitly defined by either 4 GB or TOM
minus Intel Management Engine stolen size.
Mapping steps:
1. Determine TOM
2. Determine TOM minus Intel ME stolen size
3. Determine MMIO allocation
4. Determine TOLUD
5. Determine graphics stolen base
6. Determine graphics GTT stolen base
7. Determine TSEG base
8. Determine remap base/limit
9. Determine TOUUD
The following diagrams show the three possible general cases of remapping.
• Case 1: Less than 4 GB of Physical Memory, no remap
• Case 2: Greater than 4 GB of Physical Memory
• Case 3: 4 GB or Less of Physical Memory
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Datasheet, Volume 2
INTEL [ INTEL ]
