Processor Configuration Registers
Top of Upper Usable DRAM (TOUUD)
The Top of Upper Usable Dram (TOUUD) register reflects the total amount of
addressable DRAM. If remap is disabled, TOUUD will reflect TOM minus Intel
Management Engine stolen size. If remap is enabled, then it will reflect the remap limit.
Note:
When there is more than 4 GB of DRAM and reclaim is enabled, the reclaim base will be
the same as TOM minus Intel ME stolen memory size to the nearest 1 MB alignment
(shown in the following case 2).
Top of Low Usable DRAM (TOLUD)
TOLUD register is restricted to 4 GB memory (A[31:20]), but the processor can support
up to 32 GB, limited by DRAM pins. For physical memory greater than 4 GB, the TOUUD
register helps identify the address range in between the 4 GB boundary and the top of
physical memory. This identifies memory that can be directly accessed (including
remap address calculation), which is useful for memory access indication and early
path indication. TOLUD can be 1 MB aligned.
TSEG_BASE
The “TSEG_BASE” register reflects the total amount of low addressable DRAM, below
TOLUD. BIOS will calculate and program this register; so, the system agent has
knowledge of where (TOLUD) – (GFX stolen) – (GFX GTT stolen) – (TSEG) is located.
I/O blocks use this minus DPR for upstream DRAM decode.
2.3.4.1
Memory Re-claim Background
The following are examples of Memory Mapped I/O devices are typically located below
4 GB:
• High BIOS
• TSEG
• GFX stolen
• GTT stolen
• XAPIC
• Local APIC
• MSI Interrupts
• Mbase/Mlimit
• PMbase/PMlimit
• Memory Mapped IO space that supports only 32B addressing
The processor provides the capability to re-claim the physical memory overlapped by
the Memory Mapped IO logical address space. The MCH re-maps physical memory from
the Top of Low Memory (TOLUD) boundary up to the 4 GB boundary to an equivalent
sized logical address range located just below the Intel Management Engine stolen
memory.
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Datasheet, Volume 2
INTEL [ INTEL ]
