Processor Configuration Registers
Memory requests to this range would then be forwarded to the PCI Express port. This
mode is intended for the entry Workstation/Server SKU of the MCH, and would be
disabled in typical Desktop systems. When disabled, any access within entire APIC
Configuration space (FEC0_0000h to FECF_FFFFh) is forwarded to DMI.
2.3.3.2
2.3.3.3
HSEG (FEDA_0000h – FEDB_FFFFh)
This decode range is not supported on the processor platform.
MSI Interrupt Memory Space (FEE0_0000 – FEEF_FFFF)
Any PCI Express or DMI device may issue a Memory Write to 0FEEx_xxxxh. This
Memory Write cycle does not go to DRAM. The system agent will forward this Memory
Write along with the data to the processor as an Interrupt Message Transaction.
2.3.3.4
High BIOS Area
For security reasons, the processor will positively decode this range to DMI. This
positive decode will ensure any overlapping ranges will be ignored.
The top 2 MB (FFE0_0000h–FFFF_FFFFh) of the PCI Memory Address Range is reserved
for System BIOS (High BIOS), extended BIOS for PCI devices, and the A20 alias of the
system BIOS. The processor begins execution from the High BIOS after reset. This
region is positively decoded to DMI. The actual address space required for the BIOS is
less than 2 MB but the minimum processor MTRR range for this region is 2 MB so that
full 2 MB must be considered.
2.3.4
Main Memory Address Space (4 GB to TOUUD)
The processor supports 39-bit addressing.
The maximum main memory size supported is 32 GB total DRAM memory. A hole
between TOLUD and 4 GB occurs when main memory size approaches 4 GB or larger.
As a result, TOM, and TOUUD registers and REMAPBASE/REMAPLIMIT registers become
relevant.
The remap configuration registers exist to remap lost main memory space. The greater
than 32 bit remap handling will be handled similar to other MCHs.
Upstream read and write accesses above 39-bit addressing will be treated as invalid
cycles by PEG and DMI.
Top of Memory (TOM)
The “Top of Memory” (TOM) register reflects the total amount of populated physical
memory. This is NOT necessarily the highest main memory address (holes may exist in
main memory address map due to addresses allocated for memory mapped I/O above
TOM).
The Intel Management Engine (ME) stolen size register reflects the total amount of
physical memory stolen by the Intel Management Engine. The Intel ME stolen memory
is located at the top of physical memory. The Intel ME stolen memory base is calculated
by subtracting the amount of memory stolen by the Intel Management Engine from
TOM.
Datasheet, Volume 2
27
INTEL [ INTEL ]
