Processor Configuration Registers
2.3.2
Main Memory Address Range (1 MB – TOLUD)
This address range extends from 1 MB to the top of Low Usable physical memory that is
permitted to be accessible by the processor (as programmed in the TOLUD register).
The processor will route all addresses within this range to the DRAM unless it falls into
the optional TSEG, optional ISA Hole, or optional IGD stolen VGA memory.
Figure 2-3. Main Memory Address Range
FFFF_FFFFh
4 GB Max
FLASH
APIC
Intel® TXT
Contains:
Dev 0, 1, 2, 6, 7
BARS & PCH/PCI
ranges
PCI Memory Range
TOLUD
IGD
IGGTT
TSEG
DPR
TSEG_BASE
Main Memory
0100_0000h
00F0_0000h
16MB
15MB
ISA Hole (optional)
Main Memory
0010_0000h
0h
1MB
0MB
DOS Compatibility Memory
2.3.2.1
ISA Hole (15 MB – 16 MB)
The ISA Hole is enabled in the Legacy Access Control Register in Device 0 configuration
space. If no hole is created, the processor will route the request to DRAM. If a hole is
created, the processor will route the request to DMI, since the request does not target
DRAM.
Graphics translated requests to the range will always route to DRAM.
22
Datasheet, Volume 2
INTEL [ INTEL ]
