欢迎访问ic37.com |
会员登录 免费注册
发布采购

326769-002 参数 Datasheet PDF下载

326769-002图片预览
型号: 326769-002
PDF下载: 下载PDF文件 查看货源
内容描述: 移动第三代英特尔®科雷亚?? ¢处理器家族 [Mobile 3rd Generation Intel® Core™ Processor Family]
分类和应用:
文件页数/大小: 342 页 / 2513 K
品牌: INTEL [ INTEL ]
 浏览型号326769-002的Datasheet PDF文件第17页浏览型号326769-002的Datasheet PDF文件第18页浏览型号326769-002的Datasheet PDF文件第19页浏览型号326769-002的Datasheet PDF文件第20页浏览型号326769-002的Datasheet PDF文件第22页浏览型号326769-002的Datasheet PDF文件第23页浏览型号326769-002的Datasheet PDF文件第24页浏览型号326769-002的Datasheet PDF文件第25页  
Processor Configuration Registers  
Compatible SMRAM Address Range (A_0000h–B_FFFFh)  
When compatible SMM space is enabled, SMM-mode processor accesses to this range  
route to physical system DRAM at 000A_0000h–000B_FFFFh.  
PCI Express and DMI originated cycles to enable SMM space are not allowed and are  
considered to be to the Video Buffer Area, if IGD is not enabled as the VGA device. DMI  
initiated writes cycles are attempted as peer writes cycles to a VGA enabled PCIe port.  
Monochrome Adapter (MDA) Range (B_0000h–B_7FFFh)  
Legacy support requires the ability to have a second graphics controller (monochrome)  
in the system. Accesses in the standard VGA range are forwarded to IGD, PCI Express,  
or the DMI Interface (depending on configuration bits). Since the monochrome adapter  
may be mapped to any of these devices, the processor must decode cycles in the MDA  
range (000B_0000h–000B_7FFFh) and forward either to IGD, PCI Express, or the DMI  
Interface. This capability is controlled by the VGA steering bits and the legacy  
configuration bit (MDAP bit). In addition to the memory range B0000h to B7FFFh, the  
processor decodes I/O cycles at 3B4h, 3B5h, 3B8h, 3B9h, 3BAh and 3BFh and forwards  
them to the either IGD, PCI Express, and/or the DMI Interface.  
PEG 16-bit VGA Decode  
The PCI to PCI Bridge Architecture Specification Revision 1.2, it is required that 16-bit  
VGA decode be a feature.  
When 16-bit VGA decode is disabled, the decode of VGA I/O addresses is performed on  
10 lower bits only, essentially mapping also the aliases of the defined I/O addresses.  
2.3.1.3  
PAM (C_0000h–F_FFFFh)  
The 13 sections from 768 KB to 1 MB comprise what is also known as the PAM Memory  
Area. Each section has Read enable and Write enable attributes.  
The PAM registers are mapped in Device 0 configuration space.  
• ISA Expansion Area (C_0000h–D_FFFFh)  
• Extended System BIOS Area (E_0000h–E_FFFFh)  
• System BIOS Area (F_0000h–F_FFFFh)  
The processor decodes the core request; then routes to the appropriate destination  
(DRAM or DMI).  
Snooped accesses from PCI Express or DMI to this region are snooped on processor  
caches.  
Non-snooped accesses from PCI Express or DMI to this region are always sent to  
DRAM.  
Graphics translated requests to this region are not allowed. If such a mapping error  
occurs, the request will be routed to C_0000. Writes will have the byte enables de-  
asserted.  
Datasheet, Volume 2  
21