Processor Configuration Registers
2.16
MCHBAR Registers in Memory Controller –
Common
Table 2-19. MCHBAR Registers in Memory Controller – Common Register Address Map
Address
Offset
Register
Symbol
Register Name
Reset Value
Access
0–4FFFh
RSVD
Reserved
Address decoder Channel Configuration
0h
RO
RW-L
RW-L
RW-L
—
5000–5003h
MAD_CHNL
00000024h
00600000h
00600000h
—
5004–5007h MAD_DIMM_ch0 Address Decode Channel 0
5008–500Bh MAD_DIMM_ch1 Address Decode Channel 1
500C–505Fh
5060–5063h PM_SREF_config Self Refresh Configuration
5064–50FBh RSVD Reserved
RSVD
Reserved
000100FFh
—
RW-L
—
2.16.1
MAD_CHNL—Address Decoder Channel Configuration
Register
This register defines which channel is assigned to be channel A, channel B, and channel
C according to the rule:
size(A) ≥ size (B) ≥ size(C)
Since the processor implements only two channels, channel C is always channel 2, and
its size is always 0.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/MCHBAR_MCMAIN
5000–5003h
00000024h
RW-L
Size:
32 bits
BIOS Optimal Default
0000000h
Reset
Value
RST/
PWR
Bit
Access
Description
31:6
RO
0h
Reserved (RSVD)
Channel C assignment (CH_C)
CH_C – defines the smallest channel:
00 = Channel 0
01 = Channel 1
10 = Channel 2
5:4
3:2
1:0
RW-L
RW-L
RW-L
10b
Uncore
Uncore
Uncore
Channel B assignment (CH_B)
CH_B – defines the mid-size channel:
00 = Channel 0
01 = Channel 1
10 = Channel 2
01b
00b
Channel A assignment (CH_A)
CH_A – defines the largest channel:
00 = Channel 0
01 = Channel 1
10 = Channel 2
Datasheet, Volume 2
253
INTEL [ INTEL ]
