Processor Configuration Registers
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/DMIBAR
84–87h
0001AC41h
RW-O, RO, RW-OV
32 bits
Size:
BIOS Optimal Default
00002h
Reset
Value
RST/
PWR
Bit
Access
Description
Active State Link PM Support (ASLPMS)
L0s & L1 entry supported.
11:10
RO
11b
04h
Uncore
Uncore
Max Link Width (MLW)
This field indicates the maximum number of lanes supported for
this link.
9:4
RO
Max Link Speed (MLS)
This Reset Value reflects gen1.
Later the field may be changed by BIOS to allow gen2 subject to
Fuse enabled.
3:0
RW-OV
0001b
Uncore
Defined encodings are:
0001b = 2.5 GT/s Link speed supported
0010b = 5.0 GT/s and 2.5 GT/s Link speeds supported
2.12.25 LCTL—Link Control Register
This register allows control of PCI Express* link.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/DMIBAR
88–89h
0000h
RW, RW-V
16 bits
000h
Size:
BIOS Optimal Default
Reset
Value
RST/
PWR
Bit
Access
Description
15:10
RO
0h
0b
0h
Reserved (RSVD)
Hardware Autonomous Width Disable (HAWD)
When set, this bit disables hardware from changing the Link
width for reasons other than attempting to correct unreliable Link
operation by reducing Link width.
Devices that do not implement the ability autonomously to
change Link width are permitted to hardwire this bit to 0b.
9
8
RW
RO
Uncore
Uncore
Uncore
Reserved (RSVD)
Extended Synch (ES)
0 = Standard Fast Training Sequence (FTS).
1 = Forces the transmission of additional ordered sets when
exiting the L0s state and when in the Recovery state.
This mode provides external devices (such as logic analyzers)
monitoring the Link time to achieve bit and symbol lock before
the link enters L0 and resumes communication.
7
RW
0b
This is a test mode only and may cause other undesired side
effects such as buffer overflows or underruns.
6
5
RO
0h
0b
Reserved (RSVD)
Retrain Link (RL)
0 = Normal operation.
1 = Full Link retraining is initiated by directing the Physical Layer
LTSSM from L0, L0s, or L1 states to the Recovery state.
RW-V
This bit always returns 0 when read. This bit is cleared
automatically (no need to write a 0).
234
Datasheet, Volume 2
INTEL [ INTEL ]
