Processor Configuration Registers
2.12.22 DMILE2D—DMI Link Entry 2 Description Register
This register provides the first part of a Link Entry that declares an internal link to
another Root Complex Element.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/DMIBAR
60–63h
00000000h
RO, RW-O
32 bits
Size:
BIOS Optimal Default
0000h
Reset
Value
RST/
PWR
Bit
Access
Description
Target Port Number (TPN)
This field specifies the port number associated with the element
targeted by this link entry (Egress Port). The target port number
is with respect to the component that contains this element as
specified by the target component ID.
31:24
RO
00h
00h
Uncore
Uncore
Target Component ID (TCID)
This field identifies the physical or logical component that is
targeted by this link entry.
BIOS Requirement: This field must be initialized according to
guidelines in the PCI Express* Isochronous/Virtual Channel
Support Hardware Programming Specification (HPS).
23:16
RW-O
15:2
1
RO
RO
0h
0b
Reserved (RSVD)
Link Type (LTYP)
This field indicates that the link points to memory-mapped space
(for RCRB).
The link address specifies the 64-bit base address of the target
RCRB.
Uncore
Uncore
Link Valid (LV)
0 = Link Entry is not valid and will be ignored.
1 = Link Entry specifies a valid link.
0
RW-O
0b
232
Datasheet, Volume 2
INTEL [ INTEL ]
