Processor Configuration Registers
2.12.19 DMILE1D—DMI Link Entry 1 Description Register
This register provides the first part of a Link Entry which declares an internal link to
another Root Complex Element.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/DMIBAR
50–53h
00000000h
RW-O, RO
32 bits
Size:
BIOS Optimal Default
0000h
Reset
Value
RST/
PWR
Bit
Access
Description
Target Port Number (TPN)
This field specifies the port number associated with the element
targeted by this link entry (egress port of PCH). The target port
number is with respect to the component that contains this
element as specified by the target component ID.
This can be programmed by BIOS, but the Reset Value will likely
be correct because the DMI RCRB in the PCH will likely be
associated with the default egress port for the PCH meaning it
will be assigned port number 0.
31:24
RW-O
00h
Uncore
Uncore
Target Component ID (TCID)
Identifies the physical component that is targeted by this link
entry.
BIOS Requirement: This field must be initialized according to
guidelines in the PCI Express* Isochronous/Virtual Channel
Support Hardware Programming Specification (HPS).
23:16
RW-O
00h
15:2
1
RO
RO
0h
0b
Reserved (RSVD)
Link Type (LTYP)
This bit indicates that the link points to memory-mapped space
(for RCRB).
The link address specifies the 64-bit base address of the target
RCRB.
Uncore
Uncore
Link Valid (LV)
0 = Link Entry is not valid and will be ignored.
1 = Link Entry specifies a valid link.
0
RW-O
0b
230
Datasheet, Volume 2
INTEL [ INTEL ]
