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326769-002 参数 Datasheet PDF下载

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型号: 326769-002
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内容描述: 移动第三代英特尔®科雷亚?? ¢处理器家族 [Mobile 3rd Generation Intel® Core™ Processor Family]
分类和应用:
文件页数/大小: 342 页 / 2513 K
品牌: INTEL [ INTEL ]
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Processor Configuration Registers  
2.12.16 DMIVCMRSTS—DMI VCm Resource Status Register  
B/D/F/Type:  
Address Offset:  
Reset Value:  
Access:  
0/0/0/DMIBAR  
3E–3Fh  
0002h  
RO-V  
Size:  
16 bits  
BIOS Optimal Default  
0000h  
Reset  
Value  
RST/  
PWR  
Bit  
Access  
Description  
15:2  
RO  
0h  
1b  
0h  
Reserved (RSVD)  
Virtual Channel Negotiation Pending (VCNEGPND)  
0 = The VC negotiation is complete.  
1 = The VC resource is still in the process of negotiation  
(initialization or disabling).  
Software may use this bit when enabling or disabling the VC. This  
bit indicates the status of the process of Flow Control  
initialization. It is set by default on Reset, as well as whenever  
the corresponding Virtual Channel is Disabled or the Link is in the  
DL_Down state. It is cleared when the link successfully exits the  
FC_INIT2 state.  
Before using a Virtual Channel, software must check whether the  
VC Negotiation Pending fields for that Virtual Channel are cleared  
in both Components on a Link.  
1
RO-V  
Uncore  
0
RO  
Reserved (RSVD)  
2.12.17 DMIRCLDECH—DMI Root Complex Link Declaration  
Register  
This capability declares links from the respective element to other elements of the root  
complex component to which it belongs and to an element in another root complex  
component. See PCI Express* specification for link/topology declaration requirements.  
B/D/F/Type:  
Address Offset:  
Reset Value:  
Access:  
0/0/0/DMIBAR  
40–43h  
08010005h  
RO  
Size:  
32 bits  
Reset  
Value  
RST/  
PWR  
Bit  
Access  
Description  
Pointer to Next Capability (PNC)  
This field contains the offset to the next PCI Express capability  
structure in the linked list of capabilities (Internal Link Control  
Capability).  
31:20  
RO  
080h  
Uncore  
Link Declaration Capability Version (LDCV)  
Hardwired to 1 to indicate compliances with the 1.1 version of  
the PCI Express specification.  
Note: This version does not change for 2.0 compliance.  
19:16  
15:0  
RO  
RO  
1h  
Uncore  
Uncore  
Extended Capability ID (ECID)  
a value of 0005h identifies this linked list item (capability  
structure) as being for PCI Express Link Declaration Capability.  
0005h  
228  
Datasheet, Volume 2