Processor Configuration Registers
2.10.44 RCTL—Root Control Register
This register allows control of PCI Express* Root Complex specific parameters. The
system error control bits in this register determine if corresponding SERRs are
generated when our device detects an error (reported in this device's Device Status
register) or when an error message is received across the link. Reporting of SERR as
controlled by these bits takes precedence over the SERR Enable in the PCI Command
Register.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/6/0/PCI
BC–BDh
0000h
RW, RO
16 bits
000h
Size:
BIOS Optimal Default
Reset
Value
RST/
PWR
Bit
Access
Description
15:3
RO
0h
0b
0h
Reserved (RSVD)
System Error on Fatal Error Enable (SEFEE)
This bit controls the Root Complex's response to fatal errors.
0 = No SERR generated on receipt of fatal error.
1 = SERR should be generated if a fatal error is reported by any
of the devices in the hierarchy associated with this Root
Port, or by the Root Port itself.
2
RW
Uncore
1:0
RO
Reserved (RSVD)
2.10.45 LCAP2—Link Capabilities 2 Register
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/6/0/PCI
CC–CFh
00000006h
RO-V
32 bits
Size:
BIOS Optimal Default
000000h
Reset
Value
RST/
PWR
Bit
Access
Description
31:8
RO
0h
03h
0h
Reserved (RSVD)
Supported Link Speeds Vector (SLSV):
This field indicates the supported Link speed(s) of the associated
Port. For each bit, a value of 1b indicates that the corresponding
Link speed is supported; otherwise, the Link speed is not
supported.
Bit definitions are:
Bit 1 = 2.5 GT/s
Bit 2 = 5.0 GT/s
Bit 3 = 8.0 GT/s
Bits 7:4 = Reserved
Multi-Function devices associated with an Upstream Port must
report the same value in this field for all Functions.
DMI does not support this control register since it is Gen3
register.
7:1
RO-V
Uncore
0
RO
Reserved (RSVD)
202
Datasheet, Volume 2
INTEL [ INTEL ]
