Processor Configuration Registers
2.11
PCI Device 6 Extended Configuration Registers
Table 2-14. PCI Device 6 Extended Configuration Register Address Map
Address
Offset
Symbol
Register Name
Reset Value
Access
0–103h
RSVD
PVCCAP1
PVCCAP2
PVCCTL
RSVD
Reserved
0h
00000000h
00000000h
0000h
RO
RO
104–107h
108–10Bh
10C–10Dh
10E–10Fh
110–113h
114–117h
118–119h
11A–11Bh
11C–13Fh
140–143h
144–147h
148–14Fh
150–153h
154–157h
158–15Bh
15C–15Fh
160–23Fh
240–243h
244–247h
248–C33h
C34–C37h
C38–D0Bh
Port VC Capability Register 1
Port VC Capability Register 2
Port VC Control
RO
RW, RO
RO
Reserved
0h
VC0RCAP
VC0RCTL
RSVD
VC0 Resource Capability
VC0 Resource Control
Reserved
00000001h
800000FFh
0h
RO
RO, RW
RO
VC0RSTS
RSVD
VC0 Resource Status
Reserved
0002h
RO-V
RO
0h
RCLDECH
ESD
Root Complex Link Declaration Enhanced
Element Self Description
Reserved
00010005h
05000100h
0h
RO-V, RO
RO, RW-O
RO
RSVD
LE1D
Link Entry 1 Description
Reserved
00000000h
0h
RO, RW-O
RO
RSVD
LE1A
Link Entry 1 Address
Link Entry 1 Address
Reserved
00000000h
00000000h
0h
RW-O
RW-O
RO
LE1AH
RSVD
APICBASE
APICLIMIT
RSVD
APIC Base address
APIC Base address Limit
Reserved
00000000h
00000000h
—
RW
RW,
—
CMNRXERR
RSVD
Common Rx Error Register
Reserved
00000000h
0h
RW1CS
RO
PCI Express Test Modes
RO-FW,
RW
D0C–D0Fh
D10–D33h
D34–D37h
PEGTST
RSVD
00000000h
0h
Reserved
RO
PEG UPconfig/DNconfig Control
RW,
RW1CS
PEGUPDNCFG
0000001Fh
D38–D6Bh
D6C–D6Fh
D70–DBFh
DC0–DC3h
DC4–DC7h
DC8–DCBh
DCC–DCFh
DD0–DD7h
DD8–DDBh
RSVD
BGFCTL3
RSVD
Reserved
0h
RO
RW
RO
RW
RW
RO
RW
RO
RW
BGF Control 3
400204E0h
0h
Reserved
EQPRESET1_2
Equalization Preset 1/2 Register
3400FBC0h
0037100Ah
0h
EQPRESET2_3_4 Equalization Preset 2/3/4 Register
RSVD
EQPRESET6_7
RSVD
Reserved
Equalization Preset 6/7 Register
Reserved
36200E06h
0h
EQCFG
Equalization Configuration Register
00000000h
Datasheet, Volume 2
203
INTEL [ INTEL ]
