Processor Configuration Registers
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/6/0/PCI
BA–BBh
0000h
RO, RO-V, RW1C
16 bits
Size:
BIOS Optimal Default
00h
Reset
Value
RST/
PWR
Bit
Access
Description
Reserved for Command Completed (CC)
If Command Completed notification is supported (as indicated by
No Command Completed Support field of Slot Capabilities
Register), this bit is set when a hot-plug command has completed
and the Hot-Plug Controller is ready to accept a subsequent
command. The Command Completed status bit is set as an
indication to host software that the Hot-Plug Controller has
processed the previous command and is ready to receive the
next command; it provides no assurance that the action
corresponding to the command is complete.
4
RO
0b
Uncore
If Command Completed notification is not supported, this bit
must be hardwired to 0b.
Note: PCI Express* Hot-Plug is not supported on the processor.
Presence Detect Changed (PDC)
A pulse indication that the inband presence detect state has
changed
This bit is set when the value reported in Presence Detect State is
changed.
3
2
RW1C
RO
0b
0b
Uncore
Uncore
Reserved for MRL Sensor Changed (MSC)
If an MRL sensor is implemented, this bit is set when a MRL
Sensor state change is detected. If an MRL sensor is not
implemented, this bit must not be set.
Reserved for Power Fault Detected (PFD)
If a Power Controller that supports power fault detection is
implemented, this bit is set when the Power Controller detects a
power fault at this slot. Note that, depending on hardware
capability, it is possible that a power fault can be detected at any
time, independent of the Power Controller Control setting or the
occupancy of the slot. If power fault detection is not supported,
this bit must not be set.
1
0
RO
RO
0b
0b
Uncore
Uncore
Reserved for Attention Button Pressed (ABP)
If an Attention Button is implemented, this bit is set when the
attention button is pressed. If an Attention Button is not
supported, this bit must not be set.
Datasheet, Volume 2
201
INTEL [ INTEL ]
