Processor Configuration Registers
2.10.26 PM_CS—Power Management Control/Status Register
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/6/0/PCI
84–87h
00000008h
RO, RW
32 bits
000000h
Size:
BIOS Optimal Default
Reset
Value
RST/
PWR
Bit
Access
Description
31:16
RO
0h
0b
Reserved (RSVD)
PME Status (PMESTS)
This bit indicates that this device does not support PME#
generation from D3cold.
15
RO
RO
RO
Uncore
Uncore
Uncore
Data Scale (DSCALE)
This field indicates that this device does not support the power
management data register.
14:13
12:9
00b
0h
Data Select (DSEL)
This field indicates that this device does not support the power
management data register.
PME Enable (PMEE)
This bit indicates that this device does not generate PME#
assertion from any D-state.
0 = PME# generation not possible from any D State
1 = PME# generation enabled from any D State
The setting of this bit has no effect on hardware.
See PM_CAP[15:11]
8
RW
RO
0b
0h
Uncore
7:4
Reserved (RSVD)
No Soft Reset (NSR)
When set to 1 this bit indicates that the device is transitioning
from D3hot to D0 because the power state commands do not
perform an internal reset. Configuration context is preserved.
Upon transition no additional operating system intervention is
required to preserve configuration context beyond writing the
power state bits.
When clear, the devices do not perform an internal reset upon
transitioning from D3hot to D0 using software control of the
power state bits.
Regardless of this bit the devices that transition from a D3hot to
D0 by a system or bus segment reset will return to the device
state D0 uninitialized with only PME context preserved if PME is
supported and enabled.
3
2
RO
RO
1b
0h
Uncore
Reserved (RSVD)
182
Datasheet, Volume 2
INTEL [ INTEL ]
