Processor Configuration Registers
2.10.21 CAPPTR—Capabilities Pointer Register
The capabilities pointer provides the address offset to the location of the first entry in
this device's linked list of capabilities.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/6/0/PCI
34h
88h
RO
8 bits
Size:
Reset
Value
RST/
PWR
Bit
Access
Description
First Capability (CAPPTR1)
7:0
RO
88h
Uncore
The first capability in the list is the Subsystem ID and Subsystem
Vendor ID Capability.
2.10.22 INTRLINE—Interrupt Line Register
This register contains interrupt line routing information. The device itself does not use
this value; rather it is used by device drivers and operating systems to determine
priority and vector information.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/6/0/PCI
3Ch
00h
RW
8 bits
Size:
Reset
Value
RST/
PWR
Bit
Access
Description
Interrupt Connection (INTCON)
This field is used to communicate interrupt line routing
information.
BIOS Requirement: POST software writes the routing
information into this register as it initializes and configures the
system. The value indicates to which input of the system
interrupt controller this device's interrupt pin is connected.
7:0
RW
00h
Uncore
178
Datasheet, Volume 2
INTEL [ INTEL ]
