Processor Configuration Registers
2.10.29 MSI_CAPID—Message Signaled Interrupts Capability ID
Register
When a device supports MSI it can generate an interrupt request to the processor by
writing a predefined data item (a message) to a predefined memory address.
The reporting of the existence of this capability can be disabled by setting MSICH
(CAPL[0] @ 7Fh). In that case walking this linked list will skip this capability and
instead go directly from the PCI PM capability to the PCI Express* capability.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/6/0/PCI
90–91h
A005h
RO
Size:
16 bits
Reset
Value
RST/
PWR
Bit
Access
Description
Pointer to Next Capability (PNC)
15:8
RO
A0h
05h
Uncore
Uncore
This field contains a pointer to the next item in the capabilities
list which is the PCI Express capability.
Capability ID (CID)
Value of 05h identifies this linked list item (capability structure)
as being for MSI registers.
7:0
RO
2.10.30 MC—Message Control Register
System software can modify bits in this register, but the device is prohibited from doing
so.
If the device writes the same message multiple times, only one of those messages is
ensured to be serviced. If all of them must be serviced, the device must not generate
the same message again until the driver services the earlier one.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/6/0/PCI
92–93h
0000h
RO, RW
16 bits
00h
Size:
BIOS Optimal Default
Reset
Value
RST/
PWR
Bit
Access
Description
15:8
RO
0h
Reserved (RSVD)
64-bit Address Capable (B64AC)
Hardwired to 0 to indicate that the function does not implement
the upper 32 bits of the Message Address register and is
incapable of generating a 64-bit memory address.
7
RO
0b
Uncore
This may need to change in future implementations when
addressable system memory exceeds the 32b/4 GB limit.
Datasheet, Volume 2
185
INTEL [ INTEL ]
