Processor Configuration Registers
2.10.25 PM_CAPID—Power Management Capabilities Register
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/6/0/PCI
80–83h
C8039001h
RO, RO-V
32 bits
Size:
Reset
Value
RST/
PWR
Bit
Access
Description
PME Support (PMES)
This field indicates the power states in which this device may
indicate PME wake using PCI Express messaging. D0, D3hot &
D3cold. This device is not required to do anything to support
D3hot & D3cold; it simply must report that those states are
supported. Refer to the PCI Power Management 1.1 specification
for encoding explanation and other power management details.
31:27
RO
19h
Uncore
D2 Power State Support (D2PSS)
26
25
RO
RO
RO
0b
0b
Uncore
Uncore
Uncore
Hardwired to 0 to indicate that the D2 power management state
is NOT supported.
D1 Power State Support (D1PSS)
Hardwired to 0 to indicate that the D1 power management state
is NOT supported.
Auxiliary Current (AUXC)
Hardwired to 0 to indicate that there are no 3.3Vaux auxiliary
current requirements.
24:22
000b
Device Specific Initialization (DSI)
21
20
19
RO
RO
RO
0b
0b
0b
Uncore
Uncore
Uncore
Hardwired to 0 to indicate that special initialization of this device
is NOT required before generic class device driver is to use it.
Auxiliary Power Source (APS)
Hardwired to 0.
PME Clock (PMECLK)
Hardwired to 0 to indicate this device does NOT support PME#
generation.
PCI PM CAP Version (PCIPMCV)
A value of 011b indicates that this function complies with revision
1.2 of the PCI Power Management Interface Specification. --Was
Previously Hardwired to 02h to indicate there are 4 bytes of
power management registers implemented and that this device
complies with revision 1.1 of the PCI Power Management
Interface Specification.
18:16
RO
011b
Uncore
Pointer to Next Capability (PNC)
This contains a pointer to the next item in the capabilities list. If
MSICH (CAPL[0] @ 7Fh) is 0, then the next item in the
capabilities list is the Message Signaled Interrupts (MSI)
capability at 90h. If MSICH (CAPL[0] @ 7Fh) is 1, then the next
item in the capabilities list is the PCI Express capability at A0h.
15:8
7:0
RO-V
RO
90h
01h
Uncore
Uncore
Capability ID (CID)
Value of 01h identifies this linked list item (capability structure)
as being for PCI Power Management registers.
Datasheet, Volume 2
181
INTEL [ INTEL ]
