Processor Configuration Registers
2.8.11
GMADR—Graphics Memory Range Address Register
GMADR is the PCI aperture used by S/W to access tiled graphics surfaces in a linear
fashion.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/2/0/PCI
18–1Fh
000000000000000Ch
RW, RO, RW-L
64 bits
Size:
Reset
Value
RST/
PWR
Bit
Access
RW
Description
Reserved for Memory Base Address (RSVDRW)
Must be set to 0 since addressing above 512 GB is not supported.
FLR,
Uncore
63:39
38:29
0000000h
Memory Base Address (MBA)
set by the OS, these bits correspond to address signals 38:29.
00000000
00b
FLR,
Uncore
RW
512 MB Address Mask (ADMSK512)
This Bit is either part of the Memory Base Address (RW) or part
of the Address Mask (RO), depending on the value of MSAC[2:1].
See Section 2.8.21, “MSAC—Multi Size Aperture Control Register”
on page 159 for details.
FLR,
28
27
RW-L
RW-L
0b
0b
Uncore
256 MB Address Mask (ADMSK256)
This bit is either part of the Memory Base Address (RW) or part of
the Address Mask (RO), depending on the value of MSAC[2:1].
See Section 2.8.21, “MSAC—Multi Size Aperture Control Register”
on page 159 for details.
FLR,
Uncore
Address Mask (ADM)
Hardwired to 0s to indicate at least 128 MB address range.
26:4
3
RO
RO
000000h
1b
Uncore
Uncore
Prefetchable Memory (PREFMEM)
Hardwired to 1 to enable prefetching.
Memory Type (MEMTYP)
00 = 32-bit address.
10 = 64-bit address
2:1
0
RO
RO
10b
0b
Uncore
Uncore
Memory/IO Space (MIOS)
Hardwired to 0 to indicate memory space.
Datasheet, Volume 2
155
INTEL [ INTEL ]
