Processor Configuration Registers
2.8.12
IOBAR—I/O Base Address Register
This register provides the Base offset of the I/O registers within Device 2. Bits 15:6 are
programmable allowing the I/O Base to be located anywhere in 16bit I/O Address
Space. Bits 2:1 are fixed and return zero; bit 0 is hardwired to a one indicating that
8 bytes of I/O space are decoded. Access to the 8Bs of I/O space is allowed in PM state
D0 when I/O Enable (PCICMD bit 0) set. Access is disallowed in PM states D1–D3 or if
I/O Enable is clear or if Device 2 is turned off or if internal graphics is disabled thru the
fuse or fuse override mechanisms.
Access to this I/O BAR is independent of VGA functionality within Device 2.
If accesses to this I/O bar are allowed, then all 8, 16 or 32-bit I/O cycles from IA cores
that falls within the 8B are claimed.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/2/0/PCI
20–23h
00000001h
RW, RO
32 bits
Size:
BIOS Optimal Default
00000h
Reset
Value
RST/
PWR
Bit
Access
Description
31:16
15:6
5:3
RO
RW
RO
RO
0h
000h
0h
Reserved (RSVD)
IO Base Address (IOBASE)
Set by the OS, these bits correspond to address signals 15:6.
FLR,
Uncore
Reserved (RSVD)
Memory Type (MEMTYPE)
Hardwired to 0s to indicate 32-bit address.
2:1
00b
Uncore
Uncore
Memory/IO Space (MIOS)
Hardwired to "1" to indicate I/O space.
0
RO
1b
2.8.13
SVID2—Subsystem Vendor Identification Register
This register is used to uniquely identify the subsystem where the PCI device resides.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/2/0/PCI
2C–2Dh
0000h
RW-O
Size:
16 bits
Reset
Value
RST/
PWR
Bit
Access
Description
Subsystem Vendor ID (SUBVID)
This value is used to identify the vendor of the subsystem. This
register should be programmed by BIOS during boot-up. Once
written, this register becomes Read-only. This register can only
be cleared by a Reset.
15:0
RW-O
0000h
Uncore
156
Datasheet, Volume 2
INTEL [ INTEL ]
