Processor Configuration Registers
2.7.5
VC0RCTL—VC0 Resource Control Register
This register controls the resources associated with PCI Express* Virtual Channel 0.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/1/0–2/MMR
114–117h
800000FFh
RO, RW
Size:
32 bits
BIOS Optimal Default
000h
Reset
Value
RST/
PWR
Bit
Access
Description
VC0 Enable (VC0E)
31
RO
RO
RO
RO
1b
0h
Uncore
For VC0, this is hardwired to 1 and read only as VC0 can never be
disabled.
30:27
26:24
23:20
Reserved (RSVD)
VC0 ID (VC0ID)
Assigns a VC ID to the VC resource. For VC0, this is hardwired to
0 and read only.
000b
0h
Uncore
Reserved (RSVD)
Port Arbitration Select (PAS)
This field configures the VC resource to provide a particular Port
Arbitration service. This field is valid for RCRBs, Root Ports that
support peer to peer traffic, and Switch Ports, but not for PCI
Express Endpoint devices or Root Ports that do not support peer
to peer traffic.
19:17
RW
000b
Uncore
The permissible value of this field is a number corresponding to
one of the asserted bits in the Port Arbitration Capability field of
the VC resource.
This field does not affect the root port behavior.
16
RO
0h
Reserved (RSVD)
TC High VC0 Map (TCHVC0M)
Allow usage of high order TCs.
BIOS should keep this field zeroed to allow usage of the reserved
TC[3] for other purposes.
15:8
RW
00h
Uncore
TC/VC0 Map (TCVC0M)
This field indicates the TCs (Traffic Classes) that are mapped to
the VC resource. Bit locations within this field correspond to TC
values. For example, when bit 7 is set in this field, TC7 is mapped
to this VC resource. When more than one bit in this field is set, it
indicates that multiple TCs are mapped to the VC resource. In
order to remove one or more TCs from the TC/VC Map of an
enabled VC, software must ensure that no new or outstanding
transactions with the TC labels are targeted at the given Link.
7:1
RW
RO
7Fh
1b
Uncore
Uncore
TC0/VC0 Map (TC0VC0M)
Traffic Class 0 is always routed to VC0.
0
136
Datasheet, Volume 2
INTEL [ INTEL ]
