Processor Configuration Registers
2.7.4
VC0RCAP—VC0 Resource Capability Register
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/1/0–2/MMR
110–113h
00000001h
RO
Size:
32 bits
BIOS Optimal Default
00h
Reset
Value
RST/
PWR
Bit
Access
Description
31:24
23
RO
RO
RO
00h
0h
Uncore
Reserved for Port Arbitration Table Offset (PATO)
Reserved (RSVD)
22:16
00h
Uncore
Reserved for Maximum Time Slots (MTS)
Reject Snoop Transactions (RSNPT)
0 = Transactions with or without the No Snoop bit set within the
TLP header are allowed on this VC.
1 = When set, any transaction for which the No Snoop attribute
is applicable but is not set within the TLP Header will be
rejected as an Unsupported Request
15
RO
RO
0b
0h
Uncore
14:8
Reserved (RSVD)
Port Arbitration Capability (PAC)
This field indicates types of Port Arbitration supported by the VC
resource. This field is valid for all Switch Ports, Root Ports that
support peer-to-peer traffic, and RCRBs, but not for PCI Express
Endpoint devices or Root Ports that do not support peer-to-peer
traffic.
Each bit location within this field corresponds to a Port Arbitration
Capability defined below. When more than one bit in this field is
set, it indicates that the VC resource can be configured to provide
different arbitration services.
Software selects among these capabilities by writing to the Port
Arbitration Select field (see below).
7:0
RO
01h
Uncore
Defined bit positions are:
Bit 0
Non-configurable hardware-fixed arbitration scheme,
such as., Round Robin (RR)
Bit 1
Weighted Round Robin (WRR) arbitration with 32
phases
Bit 2
Bit 3
Bit 4
Bit 5
WRR arbitration with 64 phases
WRR arbitration with 128 phases
Time-based WRR with 128 phases
WRR arbitration with 256 phases
Bits 6-7 Reserved
Processor only supported arbitration indicates "Non-configurable
hardware-fixed arbitration scheme".
Datasheet, Volume 2
135
INTEL [ INTEL ]
