Processor Configuration Registers
2.6.36
DCTL—Device Control Register
This register provides control for PCI Express* device specific capabilities.
The error reporting enable bits are in reference to errors detected by this device, not
error messages received across the link. The reporting of error messages (ERR_CORR,
ERR_NONFATAL, ERR_FATAL) received by Root Port is controlled exclusively by Root
Port Command Register.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/1/0–2/PCI
A8–A9h
0020h
RO, RW
16 bits
0h
Size:
BIOS Optimal Default
Reset
Value
RST/
PWR
Bit
Access
Description
15
14:12
11
RO
RO
RO
RO
RO
0h
000b
0b
Reserved (RSVD)
Uncore
Uncore
Reserved for Max Read Request Size (MRRS)
Reserved for Enable No Snoop (NSE)
Reserved (RSVD)
10:5
4
0h
0b
Uncore
Uncore
Reserved for Enable Relaxed Ordering (ROE)
Unsupported Request Reporting Enable (URRE)
When set, this bit allows signaling ERR_NONFATAL, ERR_FATAL,
or ERR_CORR to the Root Control register when detecting an
unmasked Unsupported Request (UR). An ERR_CORR is signaled
when an unmasked Advisory Non-Fatal UR is received. An
ERR_FATAL or ERR_NONFATAL is sent to the Root Control register
when an uncorrectable non-Advisory UR is received with the
severity bit set in the Uncorrectable Error Severity register.
3
RW
0b
Fatal Error Reporting Enable (FERE)
When set, this bit enables signaling of ERR_FATAL to the Root
Control register due to internally detected errors or error
messages received across the link. Other bits also control the full
scope of related error reporting.
2
1
0
RW
RW
RW
0b
0b
0b
Uncore
Uncore
Uncore
Non-Fatal Error Reporting Enable (NERE)
When set, this bit enables signaling of ERR_NONFATAL to the
Root Control register due to internally detected errors or error
messages received across the link. Other bits also control the full
scope of related error reporting.
Correctable Error Reporting Enable (CERE)
When set, this bit enables signaling of ERR_CORR to the Root
Control register due to internally detected errors or error
messages received across the link. Other bits also control the full
scope of related error reporting.
112
Datasheet, Volume 2
INTEL [ INTEL ]
