Processor Configuration Registers
2.6.38
LCAP—Link Capabilities Register
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/1/0–2/PCI
AC–AFh
0261CD03h
RO, RO-V, RW-O, RW-OV
32 bits
Size:
Reset
Value
RST/
PWR
Bit
Access
Description
Port Number (PN)
This field indicates the PCI Express port number for the given PCI
Express link. Matches the value in Element Self
Description[31:24].
The value if this field differs between root ports
2h = Device 1 function 0
31:24
RO
02h
Uncore
3h = Device 1 function 1
4h = Device 1 function 2
5h = Device 6 function 0
23
22
RO
RO
0h
1b
Reserved (RSVD)
ASPM Optionality Compliance (AOC)
This bit must be set to 1b in all Functions. Components
implemented against certain earlier versions of this specification
will have this bit set to 0b. Software is permitted to use the value
of this bit to help determine whether to enable ASPM or whether
to run ASPM compliance tests.
Uncore
Uncore
Link Bandwidth Notification Capability (LBNC)
A value of 1b indicates support for the Link Bandwidth
Notification status and interrupt mechanisms. This capability is
required for all Root Ports and Switch downstream ports
supporting Links wider than x1 and/or multiple Link speeds.
This field is not applicable and is reserved for Endpoint devices,
PCI Express to PCI/PCI-X bridges, and Upstream Ports of
Switches.
21
RO
1b
Devices that do not implement the Link Bandwidth Notification
capability must hardwire this bit to 0b.
Data Link Layer Link Active Reporting Capable (DLLLARC)
For a Downstream Port, this bit must be set to 1b if the
component supports the optional capability of reporting the
DL_Active state of the Data Link Control and Management State
Machine. For a hot-plug capable Downstream Port (as indicated
by the Hot-Plug Capable field of the Slot Capabilities register),
this bit must be set to 1b.
For Upstream Ports and components that do not support this
optional capability, this bit must be hardwired to 0b.
Note: PCI Express* Hot-Plug is not supported on the processor.
20
19
RO
RO
0b
0b
Uncore
Uncore
Surprise Down Error Reporting Capable (SDERC)
For a Downstream Port, this bit must be set to 1b if the
component supports the optional capability of detecting and
reporting a Surprise Down error condition.
For Upstream Ports and components that do not support this
optional capability, this bit must be hardwired to 0b.
114
Datasheet, Volume 2
INTEL [ INTEL ]
