Processor Configuration Registers
2.6.29
MSI_CAPID—Message Signaled Interrupts Capability ID
Register
When a device supports MSI it can generate an interrupt request to the processor by
writing a predefined data item (a message) to a predefined memory address.
The reporting of the existence of this capability can be disabled by setting MSICH
(CAPL[0] @ 7Fh). In that case walking this linked list will skip this capability and
instead go directly from the PCI PM capability to the PCI Express capability.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/1/0–2/PCI
90–91h
A005h
RO
Size:
16 bits
Reset
Value
RST/
PWR
Bit
Access
Description
Pointer to Next Capability (PNC)
15:8
RO
A0h
05h
Uncore
Uncore
This field contains a pointer to the next item in the capabilities
list which is the PCI Express capability.
Capability ID (CID)
Value of 05h identifies this linked list item (capability structure)
as being for MSI registers.
7:0
RO
108
Datasheet, Volume 2
INTEL [ INTEL ]
