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326769-002 参数 Datasheet PDF下载

326769-002图片预览
型号: 326769-002
PDF下载: 下载PDF文件 查看货源
内容描述: 移动第三代英特尔®科雷亚?? ¢处理器家族 [Mobile 3rd Generation Intel® Core™ Processor Family]
分类和应用:
文件页数/大小: 342 页 / 2513 K
品牌: INTEL [ INTEL ]
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Processor Configuration Registers  
B/D/F/Type:  
Address Offset:  
Reset Value:  
Access:  
0/1/0–2/PCI  
80–83h  
C8039001h  
RO, RO-V  
32 bits  
Size:  
Reset  
Value  
RST/  
PWR  
Bit  
Access  
Description  
Auxiliary Current (AUXC)  
24:22  
RO  
000b  
Uncore  
Hardwired to 0 to indicate that there are no 3.3Vaux auxiliary  
current requirements.  
Device Specific Initialization (DSI)  
21  
20  
19  
RO  
RO  
RO  
0b  
0b  
0b  
Uncore  
Uncore  
Uncore  
Hardwired to 0 to indicate that special initialization of this device  
is NOT required before generic class device driver is to use it.  
Auxiliary Power Source (APS)  
Hardwired to 0.  
PME Clock (PMECLK)  
Hardwired to 0 to indicate this device does NOT support PME#  
generation.  
PCI PM CAP Version (PCIPMCV)  
A value of 011b indicates that this function complies with  
Revision 1.2 of the PCI Power Management Interface  
Specification.  
(Was previously hardwired to 02h to indicate there are 4 bytes of  
power management registers implemented and that this device  
complies with revision 1.1 of the PCI Power Management  
Interface Specification.)  
18:16  
RO  
011b  
Uncore  
Pointer to Next Capability (PNC)  
This contains a pointer to the next item in the capabilities list. If  
MSICH (CAPL[0] @ 7Fh) is 0, then the next item in the  
capabilities list is the Message Signaled Interrupts (MSI)  
capability at 90h. If MSICH (CAPL[0] @ 7Fh) is 1, then the next  
item in the capabilities list is the PCI Express capability at A0h.  
15:8  
7:0  
RO-V  
RO  
90h  
01h  
Uncore  
Uncore  
Capability ID (CID)  
Value of 01h identifies this linked list item (capability structure)  
as being for PCI Power Management registers.  
2.6.26  
PM_CS—Power Management Control/Status Register  
B/D/F/Type:  
Address Offset:  
Reset Value:  
Access:  
0/1/0–2/PCI  
84–87h  
00000008h  
RO, RW  
32 bits  
Size:  
BIOS Optimal Default  
000000h  
Reset  
Value  
RST/  
PWR  
Bit  
Access  
Description  
31:16  
RO  
0h  
0b  
Reserved (RSVD)  
PME Status (PMESTS)  
This bit indicates that this device does not support PME#  
generation from D3cold.  
15  
RO  
RO  
RO  
Uncore  
Uncore  
Uncore  
Data Scale (DSCALE)  
This field indicates that this device does not support the power  
management data register.  
14:13  
12:9  
00b  
0h  
Data Select (DSEL)  
This field indicates that this device does not support the power  
management data register.  
Datasheet, Volume 2  
105