Processor Configuration Registers
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/1/0–2/PCI
84–87h
00000008h
RO, RW
32 bits
Size:
BIOS Optimal Default
000000h
Reset
Value
RST/
PWR
Bit
Access
Description
PME Enable (PMEE)
This bit indicates that this device does not generate PME#
assertion from any D-state.
0 = PME# generation not possible from any D State
1 = PME# generation enabled from any D State
The setting of this bit has no effect on hardware.
See PM_CAP[15:11]
8
RW
RO
0b
0h
Uncore
7:4
Reserved (RSVD)
No Soft Reset (NSR)
1 = When set to 1 this bit indicates that the device is
transitioning from D3hot to D0 because the power state
commands do not perform an internal reset. Configuration
context is preserved. Upon transition no additional operating
system intervention is required to preserve configuration
context beyond writing the power state bits.
0 = When clear the devices do not perform an internal reset
upon transitioning from D3hot to D0 using software control
of the power state bits.
Regardless of this bit, the devices that transition from a D3hot to
D0 by a system or bus segment reset will return to the device
state D0 uninitialized with only PME context preserved if PME is
supported and enabled.
3
2
RO
RO
1b
0h
Uncore
Reserved (RSVD)
Power State (PS)
This field indicates the current power state of this device and can
be used to set the device into a new power state. If software
attempts to write an unsupported state to this field, write
operation must complete normally on the bus; but the data is
discarded and no state change occurs.
00 = D0
01 = D1 (Not supported in this device.)
10 = D2 (Not supported in this device.)
11 = D3
Support of D3cold does not require any special action.
1:0
RW
00b
Uncore
While in the D3hot state, this device can only act as the target of
PCI configuration transactions (for power management control).
This device also cannot generate interrupts or respond to MMR
cycles in the D3 state. The device must return to the D0 state in
order to be fully-functional.
When the Power State is other than D0, the bridge will Master
Abort (that is, not claim) any downstream cycles (with exception
of type 0 configuration cycles). Consequently, these unclaimed
cycles will go down DMI and come back up as Unsupported
Requests, which the processor logs as Master Aborts in Device 0
PCISTS[13].
There is no additional hardware functionality required to support
these Power States.
106
Datasheet, Volume 2
INTEL [ INTEL ]
