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326769-002 参数 Datasheet PDF下载

326769-002图片预览
型号: 326769-002
PDF下载: 下载PDF文件 查看货源
内容描述: 移动第三代英特尔®科雷亚?? ¢处理器家族 [Mobile 3rd Generation Intel® Core™ Processor Family]
分类和应用:
文件页数/大小: 342 页 / 2513 K
品牌: INTEL [ INTEL ]
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Processor Configuration Registers  
2.6.24  
BCTRL—Bridge Control Register  
This register provides extensions to the PCICMD register that are specific to PCI-PCI  
bridges. The BCTRL provides additional control for the secondary interface (that is, PCI  
Express-G) as well as some bits that affect the overall behavior of the "virtual" Host-  
PCI Express bridge embedded within the processor; such as VGA compatible address  
ranges mapping.  
B/D/F/Type:  
Address Offset:  
Reset Value:  
Access:  
0/1/0–2/PCI  
3E–3Fh  
0000h  
RO, RW  
16 bits  
0h  
Size:  
BIOS Optimal Default  
Reset  
Value  
RST/  
PWR  
Bit  
15:12  
11  
Access  
RO  
Description  
0h  
0b  
Reserved (RSVD)  
Discard Timer SERR# Enable (DTSERRE)  
Not Applicable or Implemented. Hardwired to 0.  
RO  
Uncore  
Uncore  
Uncore  
Uncore  
Uncore  
Discard Timer Status (DTSTS)  
Not Applicable or Implemented. Hardwired to 0.  
10  
9
RO  
RO  
RO  
RO  
0b  
0b  
0b  
0b  
Secondary Discard Timer (SDT)  
Not Applicable or Implemented. Hardwired to 0.  
Primary Discard Timer (PDT)  
Not Applicable or Implemented. Hardwired to 0.  
8
Fast Back-to-Back Enable (FB2BEN)  
Not Applicable or Implemented. Hardwired to 0.  
7
Secondary Bus Reset (SRESET)  
Setting this bit triggers a hot reset on the corresponding PCI  
Express Port. This will force the LTSSM to transition to the Hot  
Reset state (using Recovery) from L0, L0s, or L1 states.  
6
5
RW  
RO  
0b  
0b  
Uncore  
Uncore  
Master Abort Mode (MAMODE)  
Does not apply to PCI Express. Hardwired to 0.  
VGA 16-bit Decode (VGA16D)  
Enables the PCI-to-PCI bridge to provide 16-bit decoding of VGA  
I/O address precluding the decoding of alias addresses every  
1 KB. This bit only has meaning if bit 3 (VGA Enable) of this  
register is also set to 1, enabling VGA I/O decoding and  
forwarding by the bridge.  
0 = Execute 10-bit address decodes on VGA I/O accesses.  
1 = Execute 16-bit address decodes on VGA I/O accesses.  
4
3
RW  
RW  
0b  
0b  
Uncore  
Uncore  
VGA Enable (VGAEN)  
This bit controls the routing of processor initiated transactions  
targeting VGA compatible I/O and memory address ranges. See  
the VGAEN/MDAP table in Device 0, offset 97h[0].  
Datasheet, Volume 2  
103