Processor Configuration Registers
2.6.20
PMLIMITU—Prefetchable Memory Limit Address Upper
Register
The functionality associated with this register is present in the PEG design
implementation.
This register in conjunction with the corresponding Upper Limit Address register
controls the processor to PCI Express-G prefetchable memory access routing based on
the following formula:
PREFETCHABLE_MEMORY_BASE ≤ address ≤ PREFETCHABLE_MEMORY_LIMIT
The upper 12 bits of this register are read/write and correspond to address bits
A[31:20] of the 39-bit address. The lower 7 bits of the Upper Limit Address register are
read/write and correspond to address bits A[38:32] of the 39-bit address. This register
must be initialized by the configuration software. For the purpose of address decode,
address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined memory
address range will be at the top of a 1 MB aligned memory block.
Note:
Prefetchable memory range is supported to allow segregation by the configuration
software between the memory ranges that must be defined as UC and the ones that
can be designated as a USWC (that is, prefetchable) from the processor perspective.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/1/0–2/PCI
2C–2Fh
00000000h
RW
32 bits
Size:
Reset
Value
RST/
PWR
Bit
Access
Description
Prefetchable Memory Address Limit (PMLIMITU)
This field corresponds to A[63:32] of the upper limit of the
prefetchable Memory range that will be passed to PCI Express-
G.
31:0
RW
00000000h
Uncore
2.6.21
CAPPTR—Capabilities Pointer Register
The capabilities pointer provides the address offset to the location of the first entry in
this device's linked list of capabilities.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/1/0–2/PCI
34h
88h
RO
Size:
8 bits
Reset
Value
RST/
PWR
Bit
Access
Description
First Capability (CAPPTR1)
7:0
RO
88h
Uncore
The first capability in the list is the Subsystem ID and Subsystem
Vendor ID Capability.
Datasheet, Volume 2
101
INTEL [ INTEL ]
