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326769-002 参数 Datasheet PDF下载

326769-002图片预览
型号: 326769-002
PDF下载: 下载PDF文件 查看货源
内容描述: 移动第三代英特尔®科雷亚?? ¢处理器家族 [Mobile 3rd Generation Intel® Core™ Processor Family]
分类和应用:
文件页数/大小: 342 页 / 2513 K
品牌: INTEL [ INTEL ]
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Processor Configuration Registers  
2.6.17  
PMBASE—Prefetchable Memory Base Address Register  
This register in conjunction with the corresponding Upper Base Address register  
controls the processor to PCI Express-G prefetchable memory access routing based on  
the following formula:  
PREFETCHABLE_MEMORY_BASE address PREFETCHABLE_MEMORY_LIMIT  
The upper 12 bits of this register are read/write and correspond to address bits  
A[31:20] of the 40-bit address. The lower 8 bits of the Upper Base Address register are  
read/write and correspond to address bits A[39:32] of the 40-bit address. This register  
must be initialized by the configuration software. For the purpose of address decode,  
address bits A[19:0] are assumed to be 0. Thus, the bottom of the defined memory  
address range will be aligned to a 1 MB boundary.  
B/D/F/Type:  
Address Offset:  
Reset Value:  
Access:  
0/1/0–2/PCI  
24–25h  
FFF1h  
RO, RW  
16 bits  
Size:  
Reset  
Value  
RST/  
PWR  
Bit  
Access  
Description  
Prefetchable Memory Base Address (PMBASE)  
15:4  
RW  
FFFh  
1h  
Uncore  
Uncore  
This field corresponds to A[31:20] of the lower limit of the  
memory range that will be passed to PCI Express-G.  
64-bit Address Support (AS64)  
This field indicates that the upper 32 bits of the prefetchable  
memory region base address are contained in the Prefetchable  
Memory base Upper Address register at 28h.  
3:0  
RO  
Datasheet, Volume 2  
99