Processor Configuration Registers
2.6.18
PMLIMIT—Prefetchable Memory Limit Address Register
This register, in conjunction with the corresponding Upper Limit Address register,
controls the processor to PCI Express-G prefetchable memory access routing based on
the following formula:
PREFETCHABLE_MEMORY_BASE ≤ address ≤ PREFETCHABLE_MEMORY_LIMIT
The upper 12 bits of this register are read/write and correspond to address bits
A[31:20] of the 40-bit address. The lower 8 bits of the Upper Limit Address register are
read/write and correspond to address bits A[39:32] of the 40-bit address. This register
must be initialized by the configuration software. For the purpose of address decode,
address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined memory
address range will be at the top of a 1 MB aligned memory block.
Note:
Prefetchable memory range is supported to allow segregation by the configuration
software between the memory ranges that must be defined as UC and the ones that
can be designated as a USWC (that is, prefetchable) from the processor perspective.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/1/0–2/PCI
26–27h
0001h
RW, RO
Size:
16 bits
Reset
Value
RST/
PWR
Bit
Access
Description
Prefetchable Memory Address Limit (PMLIMIT)
15:4
RW
000h
1h
Uncore
Uncore
This field corresponds to A[31:20] of the upper limit of the
address range passed to PCI Express* graphics.
64-bit Address Support (AS64B)
This field indicates that the upper 32 bits of the prefetchable
memory region limit address are contained in the Prefetchable
Memory Base Limit Address register at 2Ch.
3:0
RO
2.6.19
PMBASEU—Prefetchable Memory Base Address Upper
Register
The functionality associated with this register is present in the PEG design
implementation. This register in conjunction with the corresponding Upper Base
Address register controls the processor to PCI Express-G prefetchable memory access
routing based on the following formula:
PREFETCHABLE_MEMORY_BASE ≤ address ≤ PREFETCHABLE_MEMORY_LIMIT
The upper 12 bits of this register are read/write and correspond to address bits
A[31:20] of the 39-bit address. The lower 7 bits of the Upper Base Address register are
read/write and correspond to address bits A[38:32] of the 39-bit address. This register
must be initialized by the configuration software. For the purpose of address decode,
address bits A[19:0] are assumed to be 0. Thus, the bottom of the defined memory
address range will be aligned to a 1 MB boundary.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/1/0–2/PCI
28–2Bh
00000000h
RW
Size:
32 bits
Reset
Value
RST/
PWR
Bit
Access
Description
Prefetchable Memory Base Address (PMBASEU)
This field corresponds to A[63:32] of the lower limit of the
prefetchable memory range that will be passed to PCI Express-G.
0000000
0h
31:0
RW
Uncore
100
Datasheet, Volume 2
INTEL [ INTEL ]
