Functional Description
5.1.7
5.1.8
IDSEL to Device Number Mapping
When addressing devices on the external PCI bus (with the PCI slots), the ICH10
asserts one address signal as an IDSEL. When accessing device 0, the ICH10 asserts
AD16. When accessing Device 1, the ICH10 asserts AD17. This mapping continues all
the way up to device 15 where the ICH10 asserts AD31. Note that the ICH10’s internal
functions (Intel High Definition Audio, USB, SATA and PCI Bridge) are enumerated like
they are off of a separate PCI bus (DMI) from the external PCI bus.
Standard PCI Bus Configuration Mechanism
The PCI Bus defines a slot based “configuration space” that allows each device to
contain up to eight functions with each function containing up to 256, 8-bit
configuration registers. The PCI Local Bus Specification, Revision 2.3 defines two bus
cycles to access the PCI configuration space: Configuration Read and Configuration
Write. Memory and I/O spaces are supported directly by the processor. Configuration
space is supported by a mapping mechanism implemented within the ICH10. The PCI
Local Bus Specification, Revision 2.3 defines two mechanisms to access configuration
space, Mechanism 1 and Mechanism 2. The ICH10 only supports Mechanism 1.
Warning:
Configuration writes to internal devices, when the devices are disabled, are invalid and
may cause undefined results.
5.2
PCI Express* Root Ports (D28:F0,F1,F2,F3,F4,F5)
There are six root ports available in ICH10. These all reside in device 28, and take
function 0 – 5. Port 1 is function 0, port 2 is function 1, port 3 is function 2, port 4 is
function 3, port 5 is function 4, and port 6 is function 5.
PCI Express Root Ports 1-4 can be statically configured as four x1 Ports or ganged
together to form one x4 port. Ports 5 and 6 can only be used as two x1 ports. The port
configuration is set by RCBA 224h [Bits 1:0] see Section 10.1.38 for more details.
5.2.1
Interrupt Generation
The root port generates interrupts on behalf of Hot-Plug and power management
events, when enabled. These interrupts can either be pin based, or can be MSIs, when
enabled.
When an interrupt is generated via the legacy pin, the pin is internally routed to the
ICH10 interrupt controllers. The pin that is driven is based upon the setting of the
chipset configuration registers. Specifically, the chipset configuration registers used are
the D28IP (Base address + 310Ch) and D28IR (Base address + 3146h) registers.
Datasheet
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INTEL [ INTEL ]
