Functional Description
5.1.2.8
Memory and I/O Decode to PCI
The PCI bridge in the ICH10 is a subtractive decode agent, which follows the
following rules when forwarding a cycle from DMI to the PCI interface:
• The PCI bridge will positively decode any memory/IO address within its window
registers, assuming PCICMD.MSE (D30:F0:Offset 04h:bit 1) is set for memory
windows and PCICMD.IOSE (D30:F0:Offset 04h:bit 0) is set for IO windows.
• The PCI bridge will subtractively decode any 64-bit memory address not claimed
by another agent, assuming PCICMD.MSE (D30:F0:Offset 04h:bit 1) is set.
• The PCI bridge will subtractively decode any 16-bit I/O address not claimed by
another agent assuming PCICMD.IOSE (D30:F0:Offset 04h:bit 0) is set.
• If BCTRL.IE (D30:F0:Offset 3Eh:bit 2) is set, the PCI bridge will not positively
forward from primary to secondary called out ranges in the IO window per PCI
Local Bus Specification (I/O transactions addressing the last 768 bytes in each, 1
KB block: offsets 100h to 3FFh). The PCI bridge will still take them subtractively
assuming the above rules.
• If BCTRL.VGAE (D30:F0:Offset 3Eh:bit 3) is set, the PCI bridge will positively
forward from primary to secondary I/O and memory ranges as called out in the PCI
Bridge Specification, assuming the above rules are met.
5.1.3
Parity Error Detection and Generation
PCI parity errors can be detected and reported. The following behavioral rules apply:
• When a parity error is detected on PCI, the bridge sets the SECSTS.DPE
(D30:F0:Offset 1Eh:bit 15).
• If the bridge is a master and BCTRL.PERE (D30:F0:Offset 3Eh:bit 0) is set and one
of the parity errors defined below is detected on PCI, then the bridge will set
SECSTS.DPD (D30:F0:Offset 1Eh:bit 8) and will also generate an internal SERR#.
— During a write cycle, the PERR# signal is active, or
— A data parity error is detected while performing a read cycle
• If an address or command parity error is detected on PCI and PCICMD.SEE
(D30:F0:Offset 04h:bit 8), BCTRL.PERE, and BCTRL.SEE (D30:F0:Offset 3Eh:bit 1)
are all set, the bridge will set PSTS.SSE (D30:F0:Offset 06h:bit 14) and generate
an internal SERR#.
• If the PSTS.SSE is set because of an address parity error and the PCICMD.SEE is
set, the bridge will generate an internal SERR#
• When bad parity is detected from DMI, bad parity will be driven on all data from the
bridge.
• When an address parity error is detected on PCI, the PCI bridge will never claim the
cycle. This is a slight deviation from the PCI bridge specification, which says that a
cycle should be claimed if BCTRL.PERE is not set. However, DMI does not have a
concept of address parity error, so claiming the cycle could result in the rest of the
system seeing a bad transaction as a good transaction.
Datasheet
95
INTEL [ INTEL ]
