Functional Description
5.1.4
5.1.5
PCIRST#
The PCIRST# pin is generated under two conditions:
• PLTRST# active
• BCTRL.SBR (D30:F0:Offset 3Eh:bit 6) set to 1
The PCIRST# pin is in the suspend well. PCIRST# should be tied to PCI bus agents, but
not other agents in the system.
Peer Cycles
The PCI bridge may be the initiator of peer cycles. Peer cycles include memory, IO, and
configuration cycle types. Peer cycles are only allowed through VC0, and are enabled
with the following bits:
• BPC.PDE (D30:F0:Offset 4Ch:bit 2) – Memory and I/O cycles
• BPC.CDE (D30:F0:Offset 4Ch:bit 1) – Configuration cycles
When enabled for peer for one of the above cycle types, the PCI bridge will perform a
peer decode to see if a peer agent can receive the cycle. When not enabled, memory
cycles (posted and/or non-posted) are sent to DMI, and I/O and/or configuration cycles
are not claimed.
Configuration cycles have special considerations. Under the PCI Local Bus Specification,
these cycles are not allowed to be forwarded upstream through a bridge. However, to
enable things such as manageability, BPC.CDE can be set. When set, type 1 cycles are
allowed into the part. The address format of the type 1 cycle is slightly different from a
standard PCI configuration cycle to allow addressing of extended PCI space. The format
is shown in Table 5-2.
Table 5-2.
Type 1 Address Format
Bits
31:27
Definition
Reserved (same as the PCI Local Bus Specification)
Extended Configuration Address – allows addressing of up to
4K. These bits are combined with bits 7:2 to get the full
register.
26:24
23:16
15:11
10:8
7:2
Bus Number (same as the PCI Local Bus Specification)
Device Number (same as the PCI Local Bus Specification)
Function Number (same as the PCI Local Bus Specification)
Register (same as the PCI Local Bus Specification)
0
1
Must be 1 to indicate a type 1 cycle. Type 0 cycles are not
decoded.
0
Note:
The ICH10’s USB controllers cannot perform peer-to-peer traffic.
5.1.6
PCI-to-PCI Bridge Model
From a software perspective, the ICH10 contains a PCI-to-PCI bridge. This bridge
connects DMI to the PCI bus. By using the PCI-to-PCI bridge software model, the
ICH10 can have its decode ranges programmed by existing plug-and-play software
such that PCI ranges do not conflict with graphics aperture ranges in the Host
controller.
96
Datasheet
INTEL [ INTEL ]
