Functional Description
5.2.4.3
Attention Button Detection
When an attached device is ejected, an attention button could be pressed by the user.
This attention button press will result in a the PCI Express message
“Attention_Button_Pressed” from the device. Upon receiving this message, the root
port will set SLSTS.ABP (D28:F0/F1/F2/F3F4/F5:Offset 5Ah:bit 0).
If SLCTL.ABE (D28:F0/F1/F2/F3F4/F5:Offset 58h:bit 0) and SLCTL.HPE (D28:F0/F1/F2/
F3F4/F5:Offset 58h:bit 5) are set, the Hot-Plug controller will also generate an
interrupt. The interrupt is generated on an edge-event. For example, if SLSTS.ABP is
already set, a new interrupt will not be generated.
5.2.4.4
SMI/SCI Generation
Interrupts for Hot-Plug events are not supported on legacy operating systems. To
support Hot-Plug on non-PCI Express aware operating systems, Hot-Plug events can be
routed to generate SCI. To generate SCI, MPC.HPCE (D28:F0/F1/F2/F3F4/F5:Offset
D8h:bit 30) must be set. When set, enabled Hot-Plug events will cause SMSCS.HPCS
(D28:F0/F1/F2/F3F4/F5:Offset DCh:bit 30) to be set.
Additionally, BIOS workarounds for Hot-Plug can be supported by setting MPC.HPME
(D28:F0/F1/F2/F3F4/F5:Offset D8h:bit 1). When this bit is set, Hot-Plug events can
cause SMI status bits in SMSCS to be set. Supported Hot-Plug events and their
corresponding SMSCS bit are:
• Command Completed - SCSCS.HPCCM (D28:F0/F1/F2/F3/F4/F5:Offset DCh:bit 3)
• Presence Detect Changed - SMSCS.HPPDM (D28:F0/F1/F2/F3/F4/F5:Offset DCh:bit
1)
• Attention Button Pressed - SMSCS.HPABM (D28:F0/F1/F2/F3/F4/F5:Offset DCh:bit
2)
• Link Active State Changed - SMSCS.HPLAS (D28:F0/F1/F2/F3/F4/F5:Offset DCh:bit
4)
When any of these bits are set, SMI # will be generated. These bits are set regardless
of whether interrupts or SCI is enabled for Hot-Plug events. The SMI# may occur
concurrently with an interrupt or SCI.
5.3
Gigabit Ethernet Controller (B0:D25:F0)
The ICH10 integrates a Gigabit Ethernet Controller. The integrated Gigabit Ethernet
controller is compatible with Gigabit Ethernet PHY (Intel® 82567 Gigabit Platform LAN
Connect device). The integrated Gigabit Ethernet controller provides two interfaces:
LAN Connect Interface (LCI) for 10/100 operation and Gigabit LAN Connect Interface
(GLCI) for Gigabit Ethernet operation. The GLCI is shared with the ICH10’s PCI Express
port 6 and can be enabled via a soft strap that is stored in system SPI flash, see
Section for details.
The ICH10 integrated Gigabit Ethernet controller supports multi speed operation,
10/100/1000 MB/s. The integrated Gigabit Ethernet can operate in full-duplex at all
supported speeds or half-duplex at 10/100 MB/s, and adheres with the IEEE 802.3x
Flow Control Specification.
Note:
Gigabit Ethernet (1000Mb/s) is only supported in S0.
The controller provides a system interface via a PCI function. A full memory-mapped or
IO-mapped interface is provided to the software, along with DMA mechanisms for high
performance data transfer.
Datasheet
101
INTEL [ INTEL ]
