Functional Description
5.1.2.1
5.1.2.2
Memory Reads and Writes
The bridge bursts memory writes on PCI that are received as a single packet from DMI.
I/O Reads and Writes
The bridge generates single DW I/O read and write cycles. When the cycle completes
on the PCI bus, the bridge generates a corresponding completion on DMI. If the cycle is
retried, the cycle is kept in the down bound queue and may be passed by a postable
cycle.
5.1.2.3
5.1.2.4
Configuration Reads and Writes
The bridge generates single DW configuration read and write cycles. When the cycle
completes on the PCI bus, the bridge generates a corresponding completion. If the
cycle is retried, the cycle is kept in the down bound queue and may be passed by a
postable cycle.
Locked Cycles
The bridge propagates locks from DMI per the PCI Local Bus Specification. The PCI
bridge implements bus lock, which means the arbiter will not grant to any agent except
DMI while locked.
If a locked read results in a target or master abort, the lock is not established (as per
the PCI Local Bus Specification). Agents north of the ICH10 must not forward a
subsequent locked read to the bridge if they see the first one finish with a failed
completion.
5.1.2.5
Target / Master Aborts
When a cycle initiated by the bridge is master/target aborted, the bridge will not re-
attempt the same cycle. For multiple DW cycles, the bridge increments the address and
attempts the next DW of the transaction. For all non-postable cycles, a target abort
response packet is returned for each DW that was master or target aborted on PCI. The
bridge drops posted writes that abort.
5.1.2.6
5.1.2.7
Secondary Master Latency Timer
The bridge implements a Master Latency Timer via the SMLT register which, upon
expiration, causes the de-assertion of FRAME# at the next legal clock edge when there
is another active request to use the PCI bus.
Dual Address Cycle (DAC)
The bridge will issue full 64-bit dual address cycles for device memory-mapped
registers above 4 GB.
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Datasheet
INTEL [ INTEL ]
