®
Intel ICH10 and System Clock Domains
®
4
Intel ICH10 and System Clock
Domains
Table 4-1 shows the system clock domains. Figure 4-1 shows the assumed connection
of the various system components, including the clock generator. For complete details
of the system clocking solution, refer to the system’s clock generator component
specification.
Table 4-1.
Intel® ICH10 and System Clock Domains
Clock
Domain
Frequency
Source
Usage
ICH10
SATA_CLKP,
SATA_CLKN
Main Clock
Generator
100 MHz
Differential clock pair used for SATA.
ICH10
DMI_CLKP,
DMI_CLKN
Main Clock
Generator
100 MHz
33 MHz
Differential clock pair used for DMI.
Free-running PCI Clock to Intel ICH10. This clock
remains on during S0 and S1 state, and is
expected to be shut off during S3 or below.
ICH10
PCICLK
Main Clock
Generator
Main Clock
Generator
PCI Bus, LPC I/F. These only go to external PCI
and LPC devices.
System PCI
33 MHz
ICH10
CLK48
Main Clock
Generator
Super I/O, USB controllers. Expected to be shut
off during S3.
48.000 MHz
ICH10
CLK14
14.31818
MHz
Main Clock
Generator
Used for ACPI timer and HPET timers. Expected
to be shut off during S3.
5 to 62.5
MHz
LAN Connect Generated by the LAN Connect component.
GLAN_CLK
SPI_CLK
Component
Expected to be shut off during S3.
17.86 MHz/
31.25 MHz
Generated by the ICH. Expected to be shut off
during S3.
ICH
Datasheet
91
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