LPC Interface Bridge Registers (D31:F0)
Bit
Description
SMBus SMI Status (SMBUS_SMI_STS) — R/WC. Software clears this bit by writing
a 1 to it.
0 = This bit is set from the 64 kHz clock domain used by the SMBus. Software must
wait at least 15.63 μs after the initial assertion of this bit before clearing it.
1 = Indicates that the SMI# was caused by:
1. The SMBus Slave receiving a message that an SMI# should be caused, or
2. The SMBALERT# signal goes active and the SMB_SMI_EN bit is set and the
SMBALERT_DIS bit is cleared, or
16
3. The SMBus Slave receiving a Host Notify message and the
HOST_NOTIFY_INTREN and
the SMB_SMI_EN bits are set, or
4. The ICH10 detecting the SMLINK_SLAVE_SMI command while in the S0 state.
SERIRQ_SMI_STS — RO.
0 = SMI# was not caused by the SERIRQ decoder.
1 = Indicates that the SMI# was caused by the SERIRQ decoder.
NOTE: This is not a sticky bit
15
14
PERIODIC_STS — R/WC. Software clears this bit by writing a 1 to it.
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set at the rate determined by the PER_SMI_SEL bits. If the
PERIODIC_EN bit (PMBASE + 30h, bit 14) is also set, the ICH10 generates an
SMI#.
TCO_STS — R/WC. Software clears this bit by writing a 1 to it.
0 = SMI# not caused by TCO logic.
1 = Indicates the SMI# was caused by the TCO logic. Note that this is not a wake
event.
13
12
Device Monitor Status (DEVMON_STS) — RO.
0 = SMI# not caused by Device Monitor.
1 = Set if bit 0 of the DEVACT_STS register (PMBASE + 44h) is set. The bit is not sticky,
so writes to this bit will have no effect.
Microcontroller SMI# Status (MCSMI_STS) — R/WC. Software clears this bit by
writing a 1 to it.
0 = Indicates that there has been no access to the power management microcontroller
range (62h or 66h).
11
1 = Set if there has been an access to the power management microcontroller range
(62h or 66h) and the Microcontroller Decode Enable #1 bit in the LPC Bridge I/O
Enables configuration register is 1 (D31:F0:Offset 82h:bit 11). Note that this
implementation assumes that the Microcontroller is on LPC. If this bit is set, and
the MCSMI_EN bit is also set, the ICH10 will generate an SMI#.
GPE0_STS — RO. This bit is a logical OR of the bits in the ALT_GP_SMI_STS register
that are also set up to cause an SMI# (as indicated by the GPI_ROUT registers) and
have the corresponding bit set in the ALT_GP_SMI_EN register. Bits that are not
routed to cause an SMI# will have no effect on this bit.
10
9
0 = SMI# was not generated by a GPI assertion.
1 = SMI# was generated by a GPI assertion.
GPE0_STS — RO. This bit is a logical OR of the bits 47:32, 14:10, 8, 6:2 and 0 in the
GPE0_STS register (PMBASE + 28h) that also have the corresponding bit set in the
GPE0_EN register (PMBASE + 2Ch).
0 = SMI# was not generated by a GPE0 event.
1 = SMI# was generated by a GPE0 event.
478
Datasheet
INTEL [ INTEL ]
