LPC Interface Bridge Registers (D31:F0)
Bit
Description
PIRQBF_ACT_STS — R/WC. PIRQ[B or F].
0 = The corresponding PCI interrupts have not been active.
1 = At least one of the corresponding PCI interrupts has been active. Clear this bit by
writing a 1 to the bit location.
7
PIRQAE_ACT_STS — R/WC. PIRQ[A or E].
0 = The corresponding PCI interrupts have not been active.
1 = At least one of the corresponding PCI interrupts has been active. Clear this bit by
writing a 1 to the bit location.
6
5:0
Reserved
13.8.3.18 PM2_CNT—Power Management 2 Control
I/O Address:
PMBASE + 50h
(ACPI PM2_CNT_BLK)
Attribute:
Size:
Usage:
R/W
8-bit
ACPI
Default Value:
Lockable:
Power Well:
00h
No
Core
Bit
Description
Reserved
7:1
0
Arbiter Disable (ARB_DIS) — R/W This bit is essentially just a scratchpad bit for
legacy software compatibility. Software typically sets this bit to 1 prior to entering a C3
or C4 state. When a transition to a C3 or C4 state occurs, ICH10 will automatically
prevent any internal or external non-Isoch bus masters from initiating any cycles up to
the (G)MCH. This blocking starts immediately upon the ICH10 sending the Go-C3
message to the (G)MCH. The blocking stops when the Ack-C2 message is received.
Note that this is not really blocking, in that messages (such as from PCI Express*) are
just queued and held pending.
13.8.3.19 C3_RES— C3 Residency Register
I/O Address:
Default Value
Lockable:
PMBASE +54h
00000000h
No
Attribute:
Size:
Usage:
RO
32-bit
ACPI/Legacy
Power Well:
Core
Software may only write this register during system initialization to set the state of the
C3_RESIDENCY_MODE bit. It must not be written while the timer is in use.
Bit
Description
31:24 Reserved
C3_RESIDENCY — RO. The value in this field increments at the same rate as the
Power Management Timer. This field increments while STP_CPU# is active (i.e., the
processor is in a C3 or C4 state). This field will roll over in the same way as the PM
Timer, however the most significant bit is NOT sticky.
23:0
Software is responsible for reading this field before performing the Lvl3/4 transition.
Software must also check for rollover if the maximum time in C3/C4 could be
exceeded.
NOTE: Hardware reset is the only reset of this counter field.
482
Datasheet
INTEL [ INTEL ]
