LPC Interface Bridge Registers (D31:F0)
13.8.3.11 SMI_EN—SMI Control and Enable Register
I/O Address:
Default Value:
Default Value:
Lockable:
PMBASE + 30h
00000000h (Consumer)
00000002h (Corporate)
No
Attribute:
Size:
R/W, R/WO, WO
32 bit
Usage:
ACPI or Legacy
Power Well:
Core
Note:
This register is symmetrical to the SMI status register.
Bit
Description
31:28 Reserved
GPIO_UNLOCK_SMI_EN— R/WO. Setting this bit will cause the Intel ICH10 to
generate an SMI# when the GPIO_UNLOCK_SMI_STS bit is set in the SMI_STS
register.
27
Once written to ‘1’, this bit can only be cleared by PLTRST#.
26:19 Reserved
INTEL_USB2_EN — R/W.
0 = Disable
18
1 = Enables Intel-Specific USB2 SMI logic to cause SMI#.
LEGACY_USB2_EN — R/W.
0 = Disable
17
1 = Enables legacy USB2 logic to cause SMI#.
16:15 Reserved
PERIODIC_EN — R/W.
0 = Disable.
14
13
1 = Enables the ICH10 to generate an SMI# when the PERIODIC_STS bit (PMBASE +
34h, bit 14) is set in the SMI_STS register (PMBASE + 34h).
TCO_EN — R/W.
0 = Disables TCO logic generating an SMI#. Note that if the NMI2SMI_EN bit is set,
SMIs that are caused by re-routed NMIs will not be gated by the TCO_EN bit. Even
if the TCO_EN bit is 0, NMIs will still be routed to cause SMIs.
1 = Enables the TCO logic to generate SMI#.
NOTE: This bit cannot be written once the TCO_LOCK bit is set.
Reserved
12
11
MCSMI_ENMicrocontroller SMI Enable (MCSMI_EN) — R/W.
0 = Disable.
1 = Enables ICH10 to trap accesses to the microcontroller range (62h or 66h) and
generate an SMI#. Note that “trapped’ cycles will be claimed by the ICH10 on PCI,
but not forwarded to LPC.
10:8
Reserved
BIOS Release (BIOS_RLS) — WO.
0 = This bit will always return 0 on reads. Writes of 0 to this bit have no effect.
1 = Enables the generation of an SCI interrupt for ACPI software when a one is written
to this bit position by BIOS software.
7
NOTE: GBL_STS being set will cause an SCI, even if the SCI_EN bit is not set.
Software must take great care not to set the BIOS_RLS bit (which causes
GBL_STS to be set) if the SCI handler is not in place.
Datasheet
475
INTEL [ INTEL ]
