LPC Interface Bridge Registers (D31:F0)
13.8.3.10 GPE0_EN—General Purpose Event 0 Enables Register
I/O Address:
PMBASE + 28h
(ACPI GPE0_BLK + 8)
Attribute:
Bits 0:32 R/W
Bits 33:63 RO
64-bit
Default Value:
Lockable:
Power Well:
0000000000000000h
No
Bits 0–7, 9, 12, 14–63 Resume,
Bits 8, 10–11, 13 RTC
Size:
Usage:
ACPI
This register is symmetrical to the General Purpose Event 0 Status Register. All the bits
in this register should be cleared to 0 based on a Power Button Override or processor
Thermal Trip event. The resume well bits are all cleared by RSMRST#. The RTC well bits
are cleared by RTCRST#.
Bit
Description
63:33
Reserved.
USB6_EN — R/W.
0 = Disable.
32
1 = Enable the setting of the USB4_STS bit to generate a wake event. The
USB6_STS bit is set anytime USB UHCI controller #6 signals a wake event.
Break events are handled via the USB interrupt.
GPIn_EN — R/W. These bits enable the corresponding GPI[n]_STS bits being set to
cause a SCI, and/or wake event. These bits are cleared by RSMRST#.
NOTE: Mapping is as follows: bit 31 corresponds to GPIO15... and bit 16
corresponds to GPIO0.
31:16
15
Reserved
USB4_EN — R/W.
0 = Disable.
14
13
12
1 = Enable the setting of the USB4_STS bit to generate a wake event. The
USB4_STS bit is set anytime USB UHCI controller #4 signals a wake event.
Break events are handled via the USB interrupt.
PME_B0_EN — R/W.
0 = Disable
1 = Enables the setting of the PME_B0_STS bit to generate a wake event and/or an
SCI or SMI#. PME_B0_STS can be a wake event from the S1–S4 states, or from
S5 (if entered via SLP_TYP and SLP_EN) or power failure, but not Power Button
Override. This bit defaults to 0.
NOTE: It is only cleared by Software or RTCRST#. It is not cleared by CF9h writes.
USB3_EN — R/W.
0 = Disable.
1 = Enable the setting of the USB3_STS bit to generate a wake event. The
USB3_STS bit is set anytime USB UHCI controller #3 signals a wake event.
Break events are handled via the USB interrupt.
PME_EN — R/W.
0 = Disable.
11
10
1 = Enables the setting of the PME_STS to generate a wake event and/or an SCI.
PME# can be a wake event from the S1 – S4 state or from S5 (if entered via
SLP_EN, but not power button override).
Reserved
Datasheet
473
INTEL [ INTEL ]
