LPC Interface Bridge Registers (D31:F0)
Bit
Description
SMBus Wake Status (SMB_WAK_STS) — R/WC. The SMBus controller can
independently cause an SMI# or SCI, so this bit does not need to do so (unlike the
other bits in this register). Software clears this bit by writing a 1 to it.
0 = Wake event Not caused by the ICH10’s SMBus logic.
1 = Set by hardware to indicate that the wake event was caused by the ICH10’s
SMBus logic.This bit will be set by the WAKE/SMI# command type, even if the
system is already awake. The SMI handler should then clear this bit.
NOTES:
1.
The SMBus controller will independently cause an SMI# so this bit does not
need to do so (unlike the other bits in this register).
7
2.
This bit is set by the SMBus slave command 01h (Wake/SMI#) even when the
system is in the S0 state. Therefore, to avoid an instant wake on subsequent
transitions to sleep states, software must clear this bit after each reception of
the Wake/SMI# command or just prior to entering the sleep state.
(Consumer Only) If SMB_WAK_STS is set due to SMBus slave receiving a
message, it will be cleared by internal logic when a THRMTRIP# event
happens or a Power Button Override event. However, THRMTRIP# or Power
Button Override event will not clear SMB_WAK_STS if it is set due to
SMBALERT# signal going active.
3.
4.
The SMBALERT_STS bit (D31:F3:I/O Offset 00h:Bit 5) should be cleared by
software before the SMB_WAK_STS bit is cleared.
TCOSCI_STS — R/WC. Software clears this bit by writing a 1 to it.
6
5
0 = TOC logic or thermal sensor logic did Not cause SCI.
1 = Set by hardware when the TCO logic or thermal sensor logic causes an SCI.
USB5_STS— R/WC. Software clears this bit by writing a 1 to it.
0 = USB UHCI controller 5 does NOT need to cause a wake.
1 = Set by hardware when USB UHCI controller 5 needs to cause a wake. Wake event
will be generated if the corresponding USB2_EN bit is set.
USB2_STS — R/WC. Software clears this bit by writing a 1 to it.
0 = USB UHCI controller 2 does Not need to cause a wake.
1 = Set by hardware when USB UHCI controller 2 needs to cause a wake. Wake event
will be generated if the corresponding USB2_EN bit is set.
4
USB1_STS — R/WC. Software clears this bit by writing a 1 to it.
0 = USB UHCI controller 1 does Not need to cause a wake.
1 = Set by hardware when USB UHCI controller 1 needs to cause a wake. Wake event
will be generated if the corresponding USB1_EN bit is set.
3
2
1
SWGPE_STS — R/WC.
The SWGPE_CTRL bit (bit 1 of GPE_CTRL reg) acts as a level input to this bit.
HOT_PLUG_STS — R/WC.
0 = This bit is cleared by writing a 1 to this bit position.
1 = When a PCI Express* Hot-Plug event occurs. This will cause an SCI if the
HOT_PLUG_EN bit is set in the GEP0_EN register.
Thermal Interrupt Status (THRM_STS) — R/WC. Software clears this bit by
writing a 1 to it.
0 = THRM# signal Not driven active as defined by the THRM_POL bit
0
1 = Set by hardware anytime the THRM# signal is driven active as defined by the
THRM_POL bit. Additionally, if the THRM_EN bit is set, then the setting of the
THRM_STS bit will also generate a power management event (SCI or SMI#).
472
Datasheet
INTEL [ INTEL ]
